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* Allow a register to be redefined multiple times in a basic block.Jakob Stoklund Olesen2010-06-161-0/+21
| | | | | | | | | | | | | | | | | | | | LiveVariableAnalysis was a bit picky about a register only being redefined once, but that really isn't necessary. Here is an example of chained INSERT_SUBREGs that we can handle now: 68 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1028<kill>, 14 register: %reg1040 +[70,134:0) 76 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1029<kill>, 13 register: %reg1040 replace range with [70,78:1) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,134:0) 0@78-(134) 1@70-(78) 84 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1030<kill>, 12 register: %reg1040 replace range with [78,86:2) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,134:0) 0@86-(134) 1@70-(78) 2@78-(86) 92 %reg1040<def> = INSERT_SUBREG %reg1040, %reg1031<kill>, 11 register: %reg1040 replace range with [86,94:3) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,94:3)[94,134:0) 0@94-(134) 1@70-(78) 2@78-(86) 3@86-(94) rdar://problem/8096390 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106152 91177308-0d34-0410-b5e6-96231b3b80d8
* modify so the test doesn't drop an output file in the test source directory.Jim Grosbach2010-06-161-1/+1
| | | | | | | The test should also likely have some FileCheck bits to validate the output(?). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106146 91177308-0d34-0410-b5e6-96231b3b80d8
* Make post-ra scheduling, anti-dep breaking, and register scavenger ↵Evan Cheng2010-06-162-1/+3
| | | | | | (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8
* Create a more targeted fix for not sinking instructions into a range where itBill Wendling2010-06-151-6/+0
| | | | | | | | | | will conflict with another live range. The place which creates this scenerio is the code in X86 that lowers a select instruction by splitting the MBBs. This eliminates the need to check from the bottom up in an MBB for live pregs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106066 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the local register allocator.Jakob Stoklund Olesen2010-06-1527-60/+3
| | | | | | Please use the fast allocator instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106051 91177308-0d34-0410-b5e6-96231b3b80d8
* Set the mtriple in some tests so that they use AAPCS.Rafael Espindola2010-06-154-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106041 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed vector widening of binary instructions that can trap. Patch by Visa ↵Mon P Wang2010-06-152-0/+45
| | | | | | Putkinen! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106038 91177308-0d34-0410-b5e6-96231b3b80d8
* fix fastisel to handle GS and FS relative pointers. Patch byChris Lattner2010-06-151-0/+6
| | | | | | | Nelson Elhage! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106031 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the arm_aapcscc marker from the tests. It is the defaultRafael Espindola2010-06-1511-25/+25
| | | | | | for the linux targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106029 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid processing early clobbers twice in RegAllocFast.Jakob Stoklund Olesen2010-06-151-0/+29
| | | | | | | | | Early clobbers defining a virtual register were first alocated to a physreg and then processed as a physreg EC, spilling the virtreg. This fixes PR7382. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105998 91177308-0d34-0410-b5e6-96231b3b80d8
* Add CoalescerPair helper class.Jakob Stoklund Olesen2010-06-151-0/+41
| | | | | | | | | | | | | | | | | | | | Given a copy instruction, CoalescerPair can determine which registers to coalesce in order to eliminate the copy. It deals with all the subreg fun to determine a tuple (DstReg, SrcReg, SubIdx) such that: - SrcReg is a virtual register that will disappear after coalescing. - DstReg is a virtual or physical register whose live range will be extended. - SubIdx is 0 when DstReg is a physical register. - SrcReg can be joined with DstReg:SubIdx. CoalescerPair::isCoalescable() determines if another copy instruction is compatible with the same tuple. This fixes some NEON miscompilations where shuffles are getting coalesced as if they were copies. The CoalescerPair class will replace a lot of the spaghetti logic in JoinCopy later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105997 91177308-0d34-0410-b5e6-96231b3b80d8
* Generalize the pre-coalescing of extract_subregs feeding reg_sequences,Bob Wilson2010-06-151-2/+2
| | | | | | | | | | replacing the overly conservative checks that I had introduced recently to deal with correctness issues. This makes a pretty noticable difference in our testcases where reg_sequences are used. I've updated one test to check that we no longer emit the unnecessary subreg moves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105991 91177308-0d34-0410-b5e6-96231b3b80d8
* apparently lots of dupes.Chris Lattner2010-06-141-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105956 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a nasty bug where we were not treating available_externallyChris Lattner2010-06-141-0/+25
| | | | | | | | | | | | | symbols as declarations in the X86 backend. This would manifest on darwin x86-32 as errors like this with -fvisibility=hidden: symbol '__ZNSbIcED1Ev' can not be undefined in a subtraction expression This fixes PR7353. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105954 91177308-0d34-0410-b5e6-96231b3b80d8
* remove old test.Chris Lattner2010-06-141-30/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105953 91177308-0d34-0410-b5e6-96231b3b80d8
* rename testChris Lattner2010-06-141-0/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105952 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a missing bitcast. This code used to only handle conversions betweenBob Wilson2010-06-111-0/+19
| | | | | | | | i64 and f64 types, but now it also handle Neon vector types, so the f64 result of VMOVDRR may need to be converted to a Neon type. Radar 8084742. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105845 91177308-0d34-0410-b5e6-96231b3b80d8
* Testcase for r105741.Bill Wendling2010-06-091-0/+53
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105750 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark physregs defined by inline asm as implicit.Jakob Stoklund Olesen2010-06-091-0/+17
| | | | | | | This is a bit of a hack to make inline asm look more like call instructions. It would be better to produce correct dead flags during isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105749 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix SPU to cope with vector insertelement to an undef position.Kalle Raiskila2010-06-091-2/+13
| | | | | | | We default to inserting to lane 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105722 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle loading from/storing to undef pointers on SPU by inserting a Kalle Raiskila2010-06-091-0/+5
| | | | | | | random load/store, rather than crashing llc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105710 91177308-0d34-0410-b5e6-96231b3b80d8
* LSR needs to remember inserted instructions even in postinc mode, becauseDan Gohman2010-06-051-0/+44
| | | | | | | | there could be multiple subexpressions within a single expansion which require insert point adjustment. This fixes PR7306. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105510 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-apply 105308 with fix.Evan Cheng2010-06-041-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105502 91177308-0d34-0410-b5e6-96231b3b80d8
* More tail call removal.Dale Johannesen2010-06-042-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105485 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix normalization and de-normalization of non-affine SCEVs.Dan Gohman2010-06-041-0/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105480 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a bug during widening where we would avoid legalizing a node. When weMon P Wang2010-06-042-16/+36
| | | | | | | | | | replace an OpA with a widened OpB, it is possible to get new uses of OpA due to CSE when recursively updating nodes. Since OpA has been processed, the new uses are not examined again. The patch checks if this occurred and it it did, updates the new uses of OpA to use OpB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105453 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove more tail calls.Dale Johannesen2010-06-042-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105450 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a tail call, and move some CHECKs to theDale Johannesen2010-06-041-3/+3
| | | | | | | | functions where they belong. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105449 91177308-0d34-0410-b5e6-96231b3b80d8
* This test doesn't need the ssp attribute.Dan Gohman2010-06-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105440 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove tail call. A tail call version will follow.Dale Johannesen2010-06-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105438 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove tail call to preserve this test. A tailDale Johannesen2010-06-031-1/+1
| | | | | | | | call version will follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105422 91177308-0d34-0410-b5e6-96231b3b80d8
* Make this test not use tail calls. A tail callDale Johannesen2010-06-031-3/+3
| | | | | | | | version will follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105419 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix SimplifyDemandedBits' AssertZext logic to demand all the bits. ItDan Gohman2010-06-031-0/+22
| | | | | | | needs to demand the high bits because it's asserting that they're zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105406 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 105308.Bob Wilson2010-06-031-18/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105399 91177308-0d34-0410-b5e6-96231b3b80d8
* Machine sink could potentially sink instructions into a block where the physicalBill Wendling2010-06-032-16/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | registers it defines then interfere with an existing preg live range. For instance, if we had something like these machine instructions: BB#0 ... = imul ... EFLAGS<imp-def,dead> test ..., EFLAGS<imp-def> jcc BB#2 EFLAGS<imp-use> BB#1 ... ; fallthrough to BB#2 BB#2 ... ; No code that defines EFLAGS jcc ... EFLAGS<imp-use> Machine sink will come along, see that imul implicitly defines EFLAGS, but because it's "dead", it assumes that it can move imul into BB#2. But when it does, imul's "dead" imp-def of EFLAGS is raised from the dead (a zombie) and messes up the condition code for the jump (and pretty much anything else which relies upon it being correct). The solution is to know which pregs are live going into a basic block. However, that information isn't calculated at this point. Nor does the LiveVariables pass take into account non-allocatable physical registers. In lieu of this, we do a *very* conservative pass through the basic block to determine if a preg is live coming out of it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105387 91177308-0d34-0410-b5e6-96231b3b80d8
* One underscore, not two.Eric Christopher2010-06-031-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105379 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement expansion in type legalization for add/sub with overflow. TheEli Friedman2010-06-031-0/+42
| | | | | | | | | | | | expansion is the same as that used by LegalizeDAG. The resulting code sucks in terms of performance/codesize on x86-32 for a 64-bit operation; I haven't looked into whether different expansions might be better in general. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105378 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable machine cse of instructions which define physical registers.Evan Cheng2010-06-021-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105308 91177308-0d34-0410-b5e6-96231b3b80d8
* Fill in missing support for ISD::FEXP, ISD::FPOWI, and friends.Dan Gohman2010-06-011-1/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105283 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix handling of 'load' nodes.Kalle Raiskila2010-06-011-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105269 91177308-0d34-0410-b5e6-96231b3b80d8
* fix PR6623: when optimizing for size, don't inline memcpy/memsetsChris Lattner2010-05-311-0/+30
| | | | | | | | | | that are too large. This causes the freebsd bootloader to be too large apparently. It's unclear if this should be an -Os or -Oz thing. Thoughts welcome. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105228 91177308-0d34-0410-b5e6-96231b3b80d8
* upgrade and filecheckize this test.Chris Lattner2010-05-311-6/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105227 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove schedule-livein-copies. It's not being used.Evan Cheng2010-05-291-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105095 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR7193: if sibling call address can take a register, make sure there are ↵Evan Cheng2010-05-291-0/+16
| | | | | | enough registers available by counting inreg arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105092 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some latency computation bugs: if the use is not a machine opcode do not ↵Evan Cheng2010-05-283-15/+16
| | | | | | just return zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105061 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix more tests that depended on the default register allocator choice.Jakob Stoklund Olesen2010-05-282-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104961 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate the restriction that the array size in an alloca must be i32.Dan Gohman2010-05-282-5/+19
| | | | | | | This will help reduce the amount of casting required on 64-bit targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104911 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a -regalloc=default option that chooses a register allocator based on the -OJakob Stoklund Olesen2010-05-274-4/+4
| | | | | | | | | optimization level. This only really affects llc for now because both the llvm-gcc and clang front ends override the default register allocator. I intend to remove that code later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104904 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error.Evan Cheng2010-05-271-8/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104891 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify. Eliminate unneeded debug_loc entry.Devang Patel2010-05-261-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104785 91177308-0d34-0410-b5e6-96231b3b80d8
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