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* [Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi)Jack Carter2013-08-1513-0/+4027
| | | | | | | | | | | | | | Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188457 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r188449 as it turns out we're just missing the instructions that need ↵Craig Topper2013-08-151-8/+0
| | | | | | the v16i32/v16f32 matching. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188454 91177308-0d34-0410-b5e6-96231b3b80d8
* Clang and AArch64 backend patches to support shll/shl and vmovl instructions ↵Hao Liu2013-08-152-0/+241
| | | | | | and ACLE functions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188451 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't let isPermImmMask handle v16i32 since VPERMI doesn't match on that ↵Craig Topper2013-08-151-0/+8
| | | | | | type. Remove 128-bit vector handling from isPermImmMask too, it's covered by isPSHUFDMask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188449 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Improve legalization of vector operationsTom Stellard2013-08-141-0/+111
| | | | | | This should fix hangs in the OpenCL piglit tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188431 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsicsTom Stellard2013-08-141-0/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188430 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Convert v16i8 resource descriptors to i128Tom Stellard2013-08-142-34/+34
| | | | | | | | | | | | | Now that compute support is better on SI, we can't continue using v16i8 for descriptors since this is also a legal type in OpenCL. This patch fixes numerous hangs with the piglit OpenCL test and since we now use a target specific DAG node for LOAD_CONSTANT with the correct MemOperandFlags, this should also fix: https://bugs.freedesktop.org/show_bug.cgi?id=66805 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188429 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use i8 types for resource descriptors in testsTom Stellard2013-08-144-62/+62
| | | | | | | We switched from i32 to i8 types a while ago and the tests were never updated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188428 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2Tom Stellard2013-08-142-1/+51
| | | | | | | | | | | | Using REG_SEQUENCE for BUILD_VECTOR rather than a series of INSERT_SUBREG instructions should make it easier for the register allocator to coalasce unnecessary copies. v2: - Use an SGPR register class if all the operands of BUILD_VECTOR are SGPRs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188427 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Assign a register class to the $vaddr operand for MIMG instructionsTom Stellard2013-08-141-0/+44
| | | | | | | The previous code declared the operand as unknown:$vaddr, which made it possible for scalar registers to be used instead of vector registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188425 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Handle MSAA texture targetsTom Stellard2013-08-141-1/+1
| | | | | | | | Patch by: Marek Olšák Signed-off-by: Marek Olšák <marek.olsak@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188421 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Allow conversion between v32i8 and v8i32Tom Stellard2013-08-141-0/+21
| | | | | | | | Patch by: Marek Olšák Signed-off-by: Marek Olšák <marek.olsak@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188420 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add pattern for fp_to_uintTom Stellard2013-08-141-9/+18
| | | | | | | | | | This fixes the F2U opcode for the Mesa driver. Patch by: Marek Olšák Signed-off-by: Marek Olšák <marek.olsak@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188418 91177308-0d34-0410-b5e6-96231b3b80d8
* Actually fix PPC64 64-bit GPR inline asm constraint matchingHal Finkel2013-08-141-0/+43
| | | | | | | | | | This is a follow-up to r187693, correcting that code to request the correct register class. The previous version, with the wrong register class, was not really correcting the constraints, but rather was removing them. Coincidentally, this fixed the failing test case in r187693, but obviously created other problems. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188407 91177308-0d34-0410-b5e6-96231b3b80d8
* Let t2LDRBi8 and t2LDRBi12 have same Base PointerRenato Golin2013-08-141-0/+64
| | | | | | | | | | | | | | When determining if two different loads are from the same base address, this patch allows one load to use a t2LDRi8 address mode and another to use a t2LDRi12 address mode. The current implementation is very conservative and this allows the case of differing Thumb2 byte loads to be considered. Allowing these differing modes instead of forcing the exact same opcode is useful for situations where one opcodes loads from a base address+1 and a second opcode loads for a base address-1. Patch by Daniel Stewart. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188385 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/X86/setcc-sentinals.ll: Relax expressions for x86_64-win32.NAKAMURA Takumi2013-08-141-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188340 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Properly parse registers that appear in inline-asm constraints.Akira Hatanaka2013-08-141-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188336 91177308-0d34-0410-b5e6-96231b3b80d8
* DAG: Combine (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)Jim Grosbach2013-08-132-0/+27
| | | | | | | | | | | | | | | | | | | | | | | A common idiom is to use zero and all-ones as sentinal values and to check for both in a single conditional ("x != 0 && x != (unsigned)-1"). That generates code, for i32, like: testl %edi, %edi setne %al cmpl $-1, %edi setne %cl andb %al, %cl With this transform, we generate the simpler: incl %edi cmpl $1, %edi seta %al Similar improvements for other integer sizes and on other platforms. In general, combining the two setcc instructions into one is better. rdar://14689217 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188315 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added CMP and BLEND instructions.Elena Demikhovsky2013-08-131-0/+113
| | | | | | | Lowering for SETCC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188265 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Set scheduling preference to Sched::SourceTom Stellard2013-08-128-8/+8
| | | | | | | | | | | | | | | | | | | | | | | R600 doesn't need to do any scheduling on the SelectionDAG now that it has a very good MachineScheduler. Also, using the VLIW SelectionDAG scheduler was having a major impact on compile times. For example with the phatk kernel here are the LLVM IR to machine code compile times: With Sched::VLIW Total Compile Time: 1.4890 Seconds (User + System) SelectionDAG Instruction Scheduling: 1.1670 Seconds (User + System) With Sched::Source Total Compile Time: 0.3330 Seconds (User + System) SelectionDAG Instruction Scheduling: 0.0070 Seconds (User + System) The code ouput was identical with both schedulers. This may not be true for all programs, but it gives me confidence that there won't be much reduction, if any, in code quality by using Sched::Source. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188215 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix FileCheck --check-prefix lines.Tim Northover2013-08-127-31/+31
| | | | | | | | | | Various tests had sprung up over the years which had --check-prefix=ABC on the RUN line, but "CHECK-ABC:" later on. This happened to work before, but was strictly incorrect. FileCheck is getting stricter soon though. Patch by Ron Ofir. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188173 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Use CLC and IPM to implement memcmpRichard Sandiford2013-08-121-0/+134
| | | | | | | | For now this is restricted to fixed-length comparisons with a length in the range [1, 256], as for memcpy() and MVC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188163 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow compatible extension attributes for tail callsTim Northover2013-08-122-3/+59
| | | | | | | | If the tail-callee and caller give the same bits via the same signext/zeroext attribute then a tail-call should be allowed, since the extension has already been done by the callee. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188159 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't generate floating point stubs for mips16 code if the functionReed Kotler2013-08-111-0/+25
| | | | | | | | | | | | | is actually an instrinsic that will not occur in libc. This list here is not exhaustive but fixes the one places in test-suite where this occurs. I have filed a bug against myself to research the full list and add them to the array of such cases. In the future, actual stub generation will occur in a later phase and we won't need this code because we will know at that time during the compilation that in fact no helper function was even needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188149 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added more tests for BROADCASTElena Demikhovsky2013-08-111-0/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188148 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added VPERM* instructons and MOV* zmm-to-zmm instructions.Elena Demikhovsky2013-08-111-0/+66
| | | | | | | Added a test for shuffles using VPERM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188147 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: FMA is faster than fmul and fadd for f64Niels Ole Salscheider2013-08-101-0/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188136 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add FMA patternNiels Ole Salscheider2013-08-101-0/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188135 91177308-0d34-0410-b5e6-96231b3b80d8
* Add another intrinsic that LLVM gives an incorrect prototype to.Reed Kotler2013-08-091-0/+18
| | | | | | | | | | I need to go through all the runtime routine list and see if there are any more I need to add for mips16 floating point. Prototypes must be correct or else I don't know to add a helper function call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188106 91177308-0d34-0410-b5e6-96231b3b80d8
* [stackprotector] Simplify SP Pass so that we emit different fail basic ↵Michael Gottesman2013-08-091-0/+4
| | | | | | | | | | | | | blocks for each fail condition. This patch decouples the stack protector pass so that we can support stack protector implementations that do not use the IR level generated stack protector fail basic block. No codesize increase is caused by this change since the MI level tail merge pass properly merges together the fail condition blocks (see the updated test). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188105 91177308-0d34-0410-b5e6-96231b3b80d8
* CHECK-LABEL-ify testsStephen Lin2013-08-093-11/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188087 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing 'v' prefix in front of palignr on one of checks.Craig Topper2013-08-091-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188054 91177308-0d34-0410-b5e6-96231b3b80d8
* Set ISD::FROUND to Expand by default for all typesHal Finkel2013-08-091-0/+22
| | | | | | | | | | | For most libm ISD nodes, TargetLoweringBase::initActions sets the default scalar-type action to Expand, and leaves the vector-type action default as Legal. This is not appropriate for the new ISD::FROUND node (which no backend but PowerPC handles explicitly). Fixes PR16842. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188048 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Reapply r185872 now that the address sanitizer has been changed to ↵Arnold Schwaighofer2013-08-081-3/+4
| | | | | | | | support this." This reverts commit r187939. It broke an O0 build of a spec benchmark. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188012 91177308-0d34-0410-b5e6-96231b3b80d8
* initial draft of PPCMachObjectWriter.cppDavid Fang2013-08-081-0/+84
| | | | | | | | this records relocation entries in the mach-o object file for PIC code generation. tested on powerpc-darwin8, validated against darwin otool -rvV git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188004 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Implement fp32<->fp64 conversionsNiels Ole Salscheider2013-08-082-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187988 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Implement sint<->fp64 conversionsNiels Ole Salscheider2013-08-082-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187987 91177308-0d34-0410-b5e6-96231b3b80d8
* test commit.Andrea Di Biagio2013-08-081-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187974 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure that if we're going to attempt to add a type to a DIE thatEric Christopher2013-08-081-5/+5
| | | | | | | | | | | | the type exists. Fix up cases where we weren't checking for optional types and add an assert to addType to make sure we catch this in the future. Fix up a testcase that was using the tag for DW_TAG_array_type when it meant DW_TAG_enumeration_type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187963 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC: Map frin to round() not nearbyint() and rint()Hal Finkel2013-08-081-69/+6
| | | | | | | | | | | | | | | Making use of the recently-added ISD::FROUND, which allows for custom lowering of round(), the PPC backend will now map frin to round(). Previously, we had been using frin to lower nearbyint() (and rint() via some custom lowering to handle the extra fenv flags requirements), but only in fast-math mode because frin does not tie-to-even. Several users had complained about this behavior, and this new mapping of frin to round is certainly more appropriate (and does not require fast-math mode). In effect, this reverts r178362 (and part of r178337, replacing the nearbyint mapping with the round mapping). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187960 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r185872 now that the address sanitizer has been changed to support this.Bill Wendling2013-08-071-4/+3
| | | | | | | | | | | | | | | | | | | | | | Original commit message: Stop emitting weak symbols into the "coal" sections. The Mach-O linker has been able to support the weak-def bit on any symbol for quite a while now. The compiler however continued to place these symbols into a "coal" section, which required the linker to map them back to the base section name. Replace the sections like this: __TEXT/__textcoal_nt instead use __TEXT/__text __TEXT/__const_coal instead use __TEXT/__const __DATA/__datacoal_nt instead use __DATA/__data <rdar://problem/14265330> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187939 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512 set: Added BROADCAST instructionsElena Demikhovsky2013-08-071-0/+37
| | | | | | | with lowering logic and a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187884 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Optimize floating-point comparisons with zeroRichard Sandiford2013-08-071-0/+348
| | | | | | | | | | This follows the same lines as the integer code. In the end it seemed easier to have a second 4-bit mask in TSFlags to specify the compare-like CC values. That eats one more TSFlags bit than adding a CCHasUnordered would have done, but it feels more concise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187883 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add floating-point load-and-test instructionsRichard Sandiford2013-08-073-0/+39
| | | | | | | These instructions can also be used as comparisons with zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187882 91177308-0d34-0410-b5e6-96231b3b80d8
* Create a pattern for the "trap" instruction.Reed Kotler2013-08-071-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187863 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use VSrc_* register classes as the default classes for typesTom Stellard2013-08-061-0/+84
| | | | | | | | | | | | | | | | | Since the VSrc_* register classes contain both VGPRs and SGPRs, copies that used be emitted by isel like this: SGPR = COPY VGPR Will now be emitted like this: VSrC = COPY VGPR This patch also adds a pass that tries to identify and fix situations where a VGPR to SGPR copy may occur. Hopefully, these changes will make it impossible for the compiler to generate illegal VGPR to SGPR copies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187831 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add more special cases for opcodes to ensureSRegLimit()Tom Stellard2013-08-066-45/+45
| | | | | | Also factor out the register class lookup to its own function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187830 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info Finder|Verifier: handle DbgLoc attached to instructions.Manman Ren2013-08-064-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also remove checking of llvm.dbg.sp since it is not used in generating dwarf. Current state of Finder: DebugInfoFinder tries to list all debug info MDNodes used in a module. To list debug info MDNodes used by an instruction, DebugInfoFinder provides processDeclare, processValue and processLocation to handle DbgDeclareInst, DbgValueInst and DbgLoc attached to instructions. processModule will go through all DICompileUnits in llvm.dbg.cu and list debug info MDNodes used by the CUs. TODO: 1> Finder has a list of CUs, SPs, Types, Scopes and global variables. We need to add a list of variables that are used by DbgDeclareInst and DbgValueInst. 2> MDString fields should be null or isa<MDString> and MDNode fields should be null or isa<MDNode>. We currently use empty string or int 0 to represent null. 3> Go though Verify functions and make sure that they check field types. 4> Clean up existing testing cases to remove llvm.dbg.sp and make sure each testing case has a llvm.dbg.cu. Re-apply r187609 with fix to pass ocaml binding. vmcore.ml generates a debug location with scope being metadata !{}, in verifier we treat this as a null scope. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187812 91177308-0d34-0410-b5e6-96231b3b80d8
* Add PPC64 mulli patternHal Finkel2013-08-061-0/+16
| | | | | | | | The PPC backend had been missing a pattern to generate mulli for 64-bit multiples. We had been generating it only for 32-bit multiplies. Unfortunately, generating li + mulld unnecessarily increases register pressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187807 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Add missing patterns for i1 [s,u]int_to_fpJustin Holewinski2013-08-061-0/+37
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187800 91177308-0d34-0410-b5e6-96231b3b80d8
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