aboutsummaryrefslogtreecommitdiffstats
path: root/test/MC/Disassembler/Mips
Commit message (Collapse)AuthorAgeFilesLines
* Mips: Disassemble sign-extended 64 bit immediates properly.Benjamin Kramer2013-10-111-0/+3
| | | | | | This doesn't change the meaning of the output, but makes look right. PR17539. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192483 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed bug when generating Load Upper Immediate microMIPS instruction.Zoran Jovanovic2013-09-142-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190746 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for microMIPS DIV instructions.Zoran Jovanovic2013-09-142-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190745 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for misc microMIPS instructions.Zoran Jovanovic2013-09-142-0/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190744 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds support for microMIPS Multiply and Add/Sub instructions. ↵Vladimir Medic2013-09-062-0/+24
| | | | | | Test cases are included in patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190154 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds support for microMIPS Move to/from HI/LO instructions. Test ↵Vladimir Medic2013-09-062-0/+24
| | | | | | cases are included in patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190152 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds support for microMIPS Move Conditional instructions. Test ↵Vladimir Medic2013-09-062-0/+24
| | | | | | cases are included in patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190148 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds support for microMIPS disassembler and disassembler make ↵Vladimir Medic2013-09-062-0/+298
| | | | | | check tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190144 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Use ptr_rc to simplify definitions of base+index load/store instructions.Akira Hatanaka2013-08-285-0/+69
| | | | | | | | Also, fix predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189432 91177308-0d34-0410-b5e6-96231b3b80d8
* [tests] Cleanup initialization of test suffixes.Daniel Dunbar2013-08-161-2/+0
| | | | | | | | | | | | | | | | | - Instead of setting the suffixes in a bunch of places, just set one master list in the top-level config. We now only modify the suffix list in a few suites that have one particular unique suffix (.ml, .mc, .yaml, .td, .py). - Aside from removing the need for a bunch of lit.local.cfg files, this enables 4 tests that were inadvertently being skipped (one in Transforms/BranchFolding, a .s file each in DebugInfo/AArch64 and CodeGen/PowerPC, and one in CodeGen/SI which is now failing and has been XFAILED). - This commit also fixes a bunch of config files to use config.root instead of older copy-pasted code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188513 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix FP conditional move instructions to have explicit FP condition codeAkira Hatanaka2013-07-262-0/+36
| | | | | | | | register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187242 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix FP branch instructions to have explicit FP condition code registerAkira Hatanaka2013-07-264-0/+24
| | | | | | | | operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187238 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Print instructions "beq", "bne" and "or" using assembler pseudoAkira Hatanaka2013-07-261-0/+6
| | | | | | | | | | | | instructions "beqz", "bnez" and "move", when possible. beq $2, $zero, $L1 => beqz $2, $L1 bne $2, $zero, $L1 => bnez $2, $L1 or $2, $3, $zero => move $2, $3 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187229 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Increase the number of floating point control registers available to 32.Akira Hatanaka2013-07-014-16/+16
| | | | | | | | | Create a dedicated register class for floating point condition code registers and move FCC0 from register class CCR to the new register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185373 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips Disassembler] Have the DecodeCCRRegisterClass function use the getRegChad Rosier2013-06-264-16/+16
| | | | | | | | function to lookup the proper tablegen'ed register enumeration. Previously, it was using the encoded value directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185026 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] DSP-ASE move from HI/LO register instructions.Akira Hatanaka2013-04-181-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179739 91177308-0d34-0410-b5e6-96231b3b80d8
* Use object file specific section type for initial text sectionNico Rieck2013-04-148-8/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179494 91177308-0d34-0410-b5e6-96231b3b80d8
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-172-0/+12
| | | | | | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172685 91177308-0d34-0410-b5e6-96231b3b80d8
* reverting 172579Jack Carter2013-01-162-12/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172594 91177308-0d34-0410-b5e6-96231b3b80d8
* Akira,Jack Carter2013-01-162-0/+12
| | | | | | | | | | | | | | Hope you are feeling better. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172579 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove DOS line endings.Jakub Staszak2012-11-144-316/+316
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167968 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix disassembler test cases.Akira Hatanaka2012-11-024-24/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167326 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix check strings in test/MC/Disassembler/Mips/* and run FileCheck.Akira Hatanaka2012-07-128-760/+694
| | | | | | | | Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160143 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r158846.Akira Hatanaka2012-07-094-160/+172
| | | | | | | | Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159953 91177308-0d34-0410-b5e6-96231b3b80d8
* revert r159851.Akira Hatanaka2012-07-064-172/+160
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159854 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r158846.Akira Hatanaka2012-07-064-160/+172
| | | | | | | Include file MipsGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159851 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r158846.Akira Hatanaka2012-06-204-172/+160
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158855 91177308-0d34-0410-b5e6-96231b3b80d8
* In MipsDisassembler.cpp, instead of defining register class tables, use the onesAkira Hatanaka2012-06-204-160/+172
| | | | | | | | | | | | that are generated by TableGen and are already available in MipsGenRegisterInfo.inc. Suggested by Jakob Stoklund Olesen. Also, fix bug in function DecodeAFGR64RegisterClass. Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158846 91177308-0d34-0410-b5e6-96231b3b80d8
* Add lit.local.cfg to run the tests in test/MC/Disassembler/Mips.Akira Hatanaka2012-05-311-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157725 91177308-0d34-0410-b5e6-96231b3b80d8
* Add disassembler to MIPS. Akira Hatanaka2012-04-178-0/+2042
| | | | | | | | Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154935 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r153924. Delete test/MC/Disassembler/Mips and ↵Akira Hatanaka2012-04-038-0/+0
| | | | | | lib/Target/Mips/Disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153926 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r153924. There were buildbot failures.Akira Hatanaka2012-04-038-2042/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153925 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS disassembler support.Akira Hatanaka2012-04-038-0/+2042
Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153924 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-02-13 09:54:35 +0000