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* [SystemZ] Add tests for ALHSIK and ALGHSIKRichard Sandiford2013-07-191-0/+30
| | | | | | | | The insn definitions themselves crept into r186689, sorry. This should be the last of the distinct-ops instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186690 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add ALRK, AGLRK, SLRK and SGLRKRichard Sandiford2013-07-191-0/+24
| | | | | | | | Follows the same lines as r186686, but much more limited, since we only use ADD LOGICAL for multi-i64 additions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186689 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add AHIK and AGHIKRichard Sandiford2013-07-191-0/+30
| | | | | | | | I did these as a separate patch because it uses a slightly different form of RIE layout. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186687 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add ARK, AGRK, SRK and SGRKRichard Sandiford2013-07-191-0/+24
| | | | | | | The testsuite changes follow the same lines as for r186683. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186686 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add NGRK, OGRK and XGRKRichard Sandiford2013-07-191-0/+18
| | | | | | | Like r186683, but for 64 bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186685 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add NRK, ORK and XRKRichard Sandiford2013-07-191-0/+18
| | | | | | | | | | | | | The atomic tests assume the two-operand forms, so I've restricted them to z10. Running and-01.ll, or-01.ll and xor-01.ll for z196 as well as z10 shows why using convertToThreeAddress() is better than exposing the three-operand forms first and then converting back to two operands where possible (which is what I'd originally tried). Using the three-operand form first stops us from taking advantage of NG, OG and XG for spills. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186683 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Start adding z196 and zEC12 supportRichard Sandiford2013-07-191-1/+109
| | | | | | | | | | | | | This first step just adds definitions for SLLK, SRLK and SRAK. The next patch will actually make use of them during codegen. insn-bad.s tests that some form of error is reported when using these instructions on z10. More work is needed to get the "instruction requires: distinct-ops" that we'd ideally like, so I've stubbed that part out for now. I'll come back and make it mandatory once the necessary changes are in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186680 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add MC support for R[NOX]SBGRichard Sandiford2013-07-161-0/+63
| | | | | | | CodeGen support will come later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186401 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Allow 8-bit operands to RISBGRichard Sandiford2013-07-111-4/+4
| | | | | | | | | | | | | RISBG has three 8-bit operands (I3, I4 and I5). I'd originally restricted all three to 6 bits, since that's the only range we intended to use at the time. However, the top bit of I4 acts as a "zero" flag for RISBG, while the top bit of I3 acts as a "test" flag for RNSBG & co. This patch therefore allows them to have the full 8-bit range. I've left the fifth operand as a 6-bit value for now since the upper 2 bits have no defined meaning. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186070 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Immediate compare-and-branch supportRichard Sandiford2013-05-291-0/+192
| | | | | | | This patch adds support for the CIJ and CGIJ instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182846 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Register compare-and-branch supportRichard Sandiford2013-05-281-0/+175
| | | | | | | | | | | | | | | This patch adds support for the CRJ and CGRJ instructions. Support for the immediate forms will be a separate patch. The architecture has a large number of comparison instructions. I think it's generally better to concentrate on using the "best" comparison instruction first and foremost, then only use something like CRJ if CR really was the natual choice of comparison instruction. The patch therefore opportunistically converts separate CR and BRC instructions into a single CRJ while emitting instructions in ISelLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182764 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Make use of SUBTRACT HALFWORDRichard Sandiford2013-05-151-0/+51
| | | | | | | Thanks to Ulrich Weigand for noticing that this instruction was missing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181893 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Consolidate disassembler tests for valid input into 2 big testsRichard Sandiford2013-05-15339-6714/+6953
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181879 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add disassembler supportRichard Sandiford2013-05-14341-0/+6789
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181777 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-03-26 16:44:27 +0000