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* Add X86 BZHI instruction as well as BMI2 feature detection.Craig Topper2011-10-162-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, ↵Craig Topper2011-10-162-0/+6
| | | | | | VMREAD, and VMWRITE to remove hack from X86RecognizableInstr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142117 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand ↵Craig Topper2011-10-162-0/+18
| | | | | | 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142105 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work ↵Craig Topper2011-10-152-0/+27
| | | | | | because these are the first VEX encoded instructions to use the reg field as an opcode extension. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142082 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 ANDN instruction. Including instruction selection.Craig Topper2011-10-142-0/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141947 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 ↵Craig Topper2011-10-142-0/+15
| | | | | | processor which is gcc's name for Haswell. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141939 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r141854 because it was causing failures:Bill Wendling2011-10-132-15/+0
| | | | | | | | | | | | | | | | | http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101 --- Reverse-merging r141854 into '.': U test/MC/Disassembler/X86/x86-32.txt U test/MC/Disassembler/X86/simple-tests.txt D test/CodeGen/X86/bmi.ll U lib/Target/X86/X86InstrInfo.td U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86.td U lib/Target/X86/X86Subtarget.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141857 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 ↵Craig Topper2011-10-132-0/+15
| | | | | | processor which is gcc's name for Haswell. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141854 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for LDC/STC.Jim Grosbach2011-10-121-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
* Update test for r141704.Jim Grosbach2011-10-111-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141705 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 LZCNT instruction. Including instruction selection support.Craig Topper2011-10-112-0/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141651 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix disassembling of popcntw. Also remove some code that says it accounts ↵Craig Topper2011-10-112-0/+15
| | | | | | for 64BIT_REXW_XD not existing, but it does exist. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141642 91177308-0d34-0410-b5e6-96231b3b80d8
* Insert dummy ED table entries for pseudo-instructions.Jakob Stoklund Olesen2011-10-101-0/+4
| | | | | | | | | | The table is indexed by opcode, so simply removing pseudo-instructions creates a wrong mapping from opcode to table entry. Add a test case for xorps which has a very high opcode that exposes this problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141562 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Ivy Bridge 16-bit floating point conversion instructions for the X86 ↵Craig Topper2011-10-092-8/+56
| | | | | | disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.Craig Topper2011-10-071-0/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141358 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT.Craig Topper2011-10-072-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141354 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support in the disassembler for ignoring the L-bit on certain VEX ↵Craig Topper2011-10-042-0/+54
| | | | | | instructions. Mark instructions that have this behavior. Fixes PR10676. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141065 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for MOVBE and RDRAND instructions for the assembler and ↵Craig Topper2011-10-032-0/+45
| | | | | | disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141007 91177308-0d34-0410-b5e6-96231b3b80d8
* Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to ↵Craig Topper2011-10-032-0/+6
| | | | | | registers xmm8-xmm15 outside 64-bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140997 91177308-0d34-0410-b5e6-96231b3b80d8
* Test updates that were supposed to go with r140993.Craig Topper2011-10-031-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140994 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some Intel syntax disassembly issues with instructions that implicitly ↵Craig Topper2011-10-023-0/+168
| | | | | | use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140974 91177308-0d34-0410-b5e6-96231b3b80d8
* Special case disassembler handling of REX.B prefix on NOP instruction to ↵Craig Topper2011-10-021-0/+3
| | | | | | decode as XCHG R8D, EAX instead. Fixes PR10344. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140971 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix disassembling of INVEPT and INVVPID to take operandsCraig Topper2011-10-012-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140955 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix disassembler handling of CRC32 which is an odd instruction that uses ↵Craig Topper2011-10-012-0/+15
| | | | | | 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140954 91177308-0d34-0410-b5e6-96231b3b80d8
* Check in a patch that has already been code reviewed by Owen that I'd ↵James Molloy2011-09-282-0/+13
| | | | | | | | | | | | | forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an incorrect decoder test.Owen Anderson2011-09-261-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140579 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix VEX decoding in i386 mode. Fixes PR11008.Craig Topper2011-09-261-0/+289
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140515 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix incorrect disassembly test.Owen Anderson2011-09-231-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140423 91177308-0d34-0410-b5e6-96231b3b80d8
* Post-index loads/stores in still need to print the post-indexed immediate, ↵Owen Anderson2011-09-231-0/+7
| | | | | | even if it's zero, to distinguish them from non-post-indexed instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140420 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid ↵Owen Anderson2011-09-231-2/+2
| | | | | | testcases updated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140415 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't allow 32-bit only instructions to be disassembled in 64-bit mode. ↵Craig Topper2011-09-231-7/+4
| | | | | | Fixes part of PR10700. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140370 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix register printing in disassembling of push/pop of segment registers and ↵Craig Topper2011-09-221-0/+12
| | | | | | in/out in Intel syntax mode. Fixes PR10960 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140299 91177308-0d34-0410-b5e6-96231b3b80d8
* Print out immediate offset versions of PC-relative load/store instructions ↵Owen Anderson2011-09-212-1/+3
| | | | | | as [pc, #123] rather than simply #123. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140283 91177308-0d34-0410-b5e6-96231b3b80d8
* Port over more Thumb2 encoding tests to decoding tests.Owen Anderson2011-09-201-0/+608
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140152 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle STRT (and friends) like LDRT (and friends) for decoding purposes. ↵Owen Anderson2011-09-191-0/+150
| | | | | | Port over additional encoding tests to decoding tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140032 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a testcase for another corner-case decoding.Owen Anderson2011-09-161-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139970 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).Owen Anderson2011-09-161-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139964 91177308-0d34-0410-b5e6-96231b3b80d8
* Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's.Owen Anderson2011-09-161-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139958 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix disassembly of Thumb2 LDRSH with a #-0 offset.Owen Anderson2011-09-161-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139943 91177308-0d34-0410-b5e6-96231b3b80d8
* Port over more Thumb2 assembly tests to disassembly tests.Owen Anderson2011-09-161-0/+95
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139915 91177308-0d34-0410-b5e6-96231b3b80d8
* Port over more Thumb2 assembly tests to disassembly tests.Owen Anderson2011-09-161-22/+748
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139912 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND ↵Craig Topper2011-09-141-0/+18
| | | | | | from being recognized by disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139691 91177308-0d34-0410-b5e6-96231b3b80d8
* Make disassembling of VBLEND* print immediate as a XMM/YMM register name. ↵Craig Topper2011-09-141-0/+3
| | | | | | Fixes PR10917. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139690 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test case for PR10851.Craig Topper2011-09-141-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139689 91177308-0d34-0410-b5e6-96231b3b80d8
* Make use of Eli's FileCheck sorcery to improve this test.Owen Anderson2011-09-131-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139645 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct disassembly printing of Thumb2 post-incremented LDRD and STRD.Owen Anderson2011-09-131-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139639 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from ↵Craig Topper2011-09-131-12/+48
| | | | | | being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139588 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP ↵Owen Anderson2011-09-121-0/+5
| | | | | | either. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139542 91177308-0d34-0410-b5e6-96231b3b80d8
* Port more encoding tests to decoding tests, and correct an improper Thumb2 ↵Owen Anderson2011-09-121-0/+509
| | | | | | pre-indexed load decoding this uncovered. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139522 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix disassembling of one of the register/register forms of ↵Craig Topper2011-09-111-0/+60
| | | | | | MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
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