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* Fixed a bug in disassembly of STR_POST, where the immediate is the second ↵Johnny Chen2011-04-021-0/+3
| | | | | | | | | | | operand in am2offset; instead of the second operand in addrmode_imm12. rdar://problem/9225289 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128757 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.Johnny Chen2011-04-011-0/+13
| | | | | | | rdar://problem/9224276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128749 91177308-0d34-0410-b5e6-96231b3b80d8
* MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is ↵Johnny Chen2011-04-011-0/+17
| | | | | | | | | UNPREDICTABLE. rdar://problem/9224120 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128748 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the instruction table entries for AI1_adde_sube_s_irs multiclass ↵Johnny Chen2011-04-011-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | definition so that all the instruction have: let Inst{31-27} = 0b1110; // non-predicated Before, the ARM decoder was confusing: > 0x40 0xf3 0xb8 0x80 as: Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcs pc, r8, r0, asr #6 since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'. Now, the AR decoder behaves correctly: > 0x40 0xf3 0xb8 0x80 > END Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcshi pc, r8, r0, asr #6 > rdar://problem/9223094 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128746 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we ↵Johnny Chen2011-04-012-0/+15
| | | | | | | | | should reject the instruction as invalid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128734 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix LDRi12 immediate operand, which was changed to be the second operand in ↵Johnny Chen2011-04-011-0/+9
| | | | | | | | | $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm). rdar://problem/9219356 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128722 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test case for a malformed LDC/LDC2 instructions with PUDW = 0b0000, whichJohnny Chen2011-03-311-0/+11
| | | | | | | amounts to an UNDEFINED instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128668 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix single word and unsigned byte data transfer instruction encodings so thatJohnny Chen2011-03-311-0/+4
| | | | | | | | | Inst{4} = 0. rdar://problem/9213022 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128662 91177308-0d34-0410-b5e6-96231b3b80d8
* Add BLXi to the instruction table for disassembly purpose.Johnny Chen2011-03-311-0/+3
| | | | | | | | | A8.6.23 BLX (immediate) rdar://problem/9212921 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128644 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test case for thumb stc2 instruction.Johnny Chen2011-03-301-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128517 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test case for MSRi.Johnny Chen2011-03-291-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128494 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a thumb test file for printf (iOS 4.3).Johnny Chen2011-03-291-0/+76
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128487 91177308-0d34-0410-b5e6-96231b3b80d8
* A8.6.188 STC, STC2Johnny Chen2011-03-291-0/+6
| | | | | | | | | The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}. rdar://problem/9200661 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128478 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename invalid-VLDMSDB-arm.txt to be invalid-VLDMSDB_UPD-arm.txt.Johnny Chen2011-03-291-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128477 91177308-0d34-0410-b5e6-96231b3b80d8
* Add and modify some tests.Johnny Chen2011-03-292-2/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128476 91177308-0d34-0410-b5e6-96231b3b80d8
* Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't ↵Owen Anderson2011-03-292-4/+2
| | | | | | actually exist. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128461 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add ↵Johnny Chen2011-03-281-0/+9
| | | | | | | | | some test cases. Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128417 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed the t2PLD and friends disassembly and add two test cases.Johnny Chen2011-03-261-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128322 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test for A8.6.246 UMULL to both arm-tests.txt amd thumb-tests.txt.Johnny Chen2011-03-252-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128306 91177308-0d34-0410-b5e6-96231b3b80d8
* Add two test cases t2SMLABT and t2SMMULR for DisassembleThumb2Mul().Johnny Chen2011-03-251-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128305 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode ↵Johnny Chen2011-03-251-0/+9
| | | | | | | | | | | GPRRegClassID. Also add some test cases. rdar://problem/9189829 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128304 91177308-0d34-0410-b5e6-96231b3b80d8
* DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to ↵Johnny Chen2011-03-251-0/+6
| | | | | | | | | RegClass. Add two test cases. rdar://problem/9182892 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128299 91177308-0d34-0410-b5e6-96231b3b80d8
* A8.6.226 TBB, TBH:Johnny Chen2011-03-251-0/+6
| | | | | | | Add two test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128295 91177308-0d34-0410-b5e6-96231b3b80d8
* Modify DisassembleThumb2LdStEx() to be more robust/correct in light of ↵Johnny Chen2011-03-251-0/+6
| | | | | | | | | recent change to t2LDREX/t2STREX instructions. Add two test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128293 91177308-0d34-0410-b5e6-96231b3b80d8
* Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. ↵Johnny Chen2011-03-251-0/+3
| | | | | | | | | Modify the disassembler to handle that. rdar://problem/9184053 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128285 91177308-0d34-0410-b5e6-96231b3b80d8
* Also need to handle invalid imod values for CPS2p.Johnny Chen2011-03-251-0/+4
| | | | | | | rdar://problem/9186136 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128283 91177308-0d34-0410-b5e6-96231b3b80d8
* Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the ↵Johnny Chen2011-03-251-0/+3
| | | | | | | | | register classes were changed), modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128252 91177308-0d34-0410-b5e6-96231b3b80d8
* delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 ↵Johnny Chen2011-03-251-0/+3
| | | | | | instructions, and add a test case for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128249 91177308-0d34-0410-b5e6-96231b3b80d8
* The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been ↵Johnny Chen2011-03-241-0/+6
| | | | | | | | | | stale since the change to ("tLDMIA", "tLDMIA_UPD"). Update the conflict resolution code and add test cases for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128247 91177308-0d34-0410-b5e6-96231b3b80d8
* The ARM disassembler was confused with the 16-bit tSTMIA instruction.Johnny Chen2011-03-241-0/+3
| | | | | | | | According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available. Ignore tSTMIA for the decoder emitter and add a test case for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128246 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle the added VBICiv*i* NEON instructions, too.Johnny Chen2011-03-241-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128243 91177308-0d34-0410-b5e6-96231b3b80d8
* T2 Load/Store Multiple:Johnny Chen2011-03-241-0/+3
| | | | | | | | These instructions were changed to not embed the addressing mode within the MC instructions We also need to update the corresponding assert stmt. Also add a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128240 91177308-0d34-0410-b5e6-96231b3b80d8
* Plug a leak in the arm disassembler and put the tests back.Benjamin Kramer2011-03-242-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128238 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove these two test files as they cause llvm-i686-linux-vg_leak build to ↵Johnny Chen2011-03-242-8/+0
| | | | | | | | | fail 'test-llvm'. These two are test cases which should result in 'invalid instruction encoding' from running llvm-mc -disassemble. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128235 91177308-0d34-0410-b5e6-96231b3b80d8
* ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder ↵Johnny Chen2011-03-241-0/+3
| | | | | | | | | | was fooled. Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to the more generic ADDri/SUBri instructions, and add a test case for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128234 91177308-0d34-0410-b5e6-96231b3b80d8
* The r118201 added support for VORR (immediate). Update ↵Johnny Chen2011-03-241-0/+3
| | | | | | | | | ARMDisassemblerCore.cpp to disassemble the VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128226 91177308-0d34-0410-b5e6-96231b3b80d8
* Add comments to the handling of opcode CPS3p to reject invalid instruction ↵Johnny Chen2011-03-242-0/+8
| | | | | | | | | encoding, a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128220 91177308-0d34-0410-b5e6-96231b3b80d8
* Load/Store Multiple:Johnny Chen2011-03-241-0/+6
| | | | | | | | These instructions were changed to not embed the addressing mode within the MC instructions We also need to update the corresponding assert stmt. Also add two test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128191 91177308-0d34-0410-b5e6-96231b3b80d8
* STRT and STRBT was incorrectly tagged as IndexModeNone during the ↵Johnny Chen2011-03-241-0/+3
| | | | | | | | | refactorings (r119821). We now tag them as IndexModePost. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128189 91177308-0d34-0410-b5e6-96231b3b80d8
* The r128103 fix to cope with the removal of addressing modes from the MC ↵Johnny Chen2011-03-241-0/+3
| | | | | | | | | | | instructions were incomplete. The assert stmt needs to be updated and the operand index incrment is wrong. Fix the bad logic and add some sanity checking to detect bad instruction encoding; and add a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128186 91177308-0d34-0410-b5e6-96231b3b80d8
* Add disassembly test cases for:Johnny Chen2011-03-222-0/+6
| | | | | | | A8.6.292 VCMPE git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128120 91177308-0d34-0410-b5e6-96231b3b80d8
* LDRT and LDRBT was incorrectly tagged as IndexModeNone during the ↵Johnny Chen2011-03-221-0/+3
| | | | | | | | | | | refactorings (r119821). We now tag them as IndexModePost. This fixed http://llvm.org/bugs/show_bug.cgi?id=9530. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128113 91177308-0d34-0410-b5e6-96231b3b80d8
* Add one more test case for VFP Load/Store Multiple (vpop).Johnny Chen2011-03-221-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128106 91177308-0d34-0410-b5e6-96231b3b80d8
* A8.6.399 VSTM:Johnny Chen2011-03-221-0/+3
| | | | | | | | | | | | VFP Load/Store Multiple Instructions used to embed the IA/DB addressing mode within the MC instruction; that has been changed so that now, for example, VSTMDDB_UPD and VSTMDIA_UPD are two instructions. Update the ARMDisassemblerCore.cpp's DisassembleVFPLdStMulFrm() to reflect the change. Also add a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128103 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed an assert by the ARM disassembler for LDRD_PRE/POST.Johnny Chen2011-03-191-0/+3
| | | | | | | | | The relevant instruction table entries were changed sometime ago to no longer take <Rt2> as an operand. Modify ARMDisassemblerCore.cpp to accomodate the change and add a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127935 91177308-0d34-0410-b5e6-96231b3b80d8
* The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset.Johnny Chen2011-03-181-3/+3
| | | | | | | Remove the offending logic and update the test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127843 91177308-0d34-0410-b5e6-96231b3b80d8
* It used to be that t_addrmode_s4 was used for both:Johnny Chen2011-03-171-0/+9
| | | | | | | | | | | | o A8.6.195 STR (register) -- Encoding T1 o A8.6.193 STR (immediate, Thumb) -- Encoding T1 It has been changed so that now they use different addressing modes and thus different MC representation (Operand Infos). Modify the disassembler to reflect the change, and add relevant tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127833 91177308-0d34-0410-b5e6-96231b3b80d8
* There were two issues fixed:Johnny Chen2011-03-151-1/+7
| | | | | | | | | | | | | | | | | 1. The ARM Darwin *r9 call instructions were pseudo-ized recently. Modify the ARMDisassemblerCore.cpp file to accomodate the change. 2. The disassembler was unnecessarily adding 8 to the sign-extended imm24: imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate) // Encoding A1 It has no business doing such. Removed the offending logic. Add test cases to arm-tests.txt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127707 91177308-0d34-0410-b5e6-96231b3b80d8
* Basic sanity checks to ensure that 2- and 3-byteSean Callanan2011-03-151-0/+6
| | | | | | | | | VEX prefixes are working for triadic AVX instructions. This concludes the patch set to enable AVX support for the X86 disassebler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127647 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed an ARM disassembler bug where it does not handle STRi12 correctly ↵Johnny Chen2011-03-151-0/+12
| | | | | | | | | | | because an extra register operand was erroneously added. Remove an incorrect assert which triggers the bug. rdar://problem/9131529 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127642 91177308-0d34-0410-b5e6-96231b3b80d8
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