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* Update to LLVM 3.5a.Stephen Hines2014-04-241-1/+11
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* [mips] Print instructions "beq", "bne" and "or" using assembler pseudoAkira Hatanaka2013-07-261-5/+5
| | | | | | | | | | | | instructions "beqz", "bnez" and "move", when possible. beq $2, $zero, $L1 => beqz $2, $L1 bne $2, $zero, $L1 => bnez $2, $L1 or $2, $3, $zero => move $2, $3 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187229 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips assembler: Add branch macro definitionsJack Carter2013-05-161-1/+13
| | | | | | | | | | | | | This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows: bnez $rs,$imm => bne $rs,$zero,$imm beqz $rs,$imm => beq $rs,$zero,$imm The corresponding test cases are added. Patch by Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182040 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips assembler: Add 64 bit testing for JALJack Carter2013-04-241-39/+82
| | | | | | | Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180220 91177308-0d34-0410-b5e6-96231b3b80d8
* Use object file specific section type for initial text sectionNico Rieck2013-04-141-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179494 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips Assembler] Add alias definitions for jalJack Carter2013-03-281-1/+15
| | | | | | | | | | | | | Mips assembler allows following to be used as aliased instructions: jal $rs for jalr $rs jal $rd,$rd for jalr $rd,$rs This patch provides alias definitions in td files and test cases to show the usage. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178304 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the invalid opcode for Mips branch instructions in the assemblerJack Carter2013-03-221-12/+12
| | | | | | | | | | | | | | | | | | For mips a branch an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. Previously, the code generator did not perform the shift of the immediate branch offset which resulted in wrong instruction opcode. This patch fixes the issue. Contributor: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177687 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add definition of JALR instruction which has two register operands. ↵Akira Hatanaka2013-02-071-0/+8
| | | | | | | | | | Change the original JALR instruction with one register operand to be a pseudo-instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174657 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix encoding of BAL instruction. Also, fix assembler test case whichAkira Hatanaka2012-12-211-1/+1
| | | | | | | | was not catching the error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170953 91177308-0d34-0410-b5e6-96231b3b80d8
* The Mips standalone assembler aliased instruction support.Jack Carter2012-09-071-0/+8
| | | | | | | | | | | | | | | | The assembler can alias one instruction into another based on the operands. For example the jump instruction "J" takes and immediate operand, but if the operand is a register the assembler will change it into a jump register "JR" instruction. These changes are in the instruction td file. Test cases included Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163368 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips specific llvm assembler support for branch and jump instructions.Jack Carter2012-09-061-0/+64
Test case included. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163277 91177308-0d34-0410-b5e6-96231b3b80d8
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