aboutsummaryrefslogtreecommitdiffstats
path: root/test/MC
Commit message (Collapse)AuthorAgeFilesLines
* Add encoding tests for flds/fildsJoerg Sonnenberger2011-04-152-0/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129589 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-1/+1
| | | | | | | | Luis Felipe Strano Moraes! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
* The ARM disassembler did not handle the alignment correctly for VLD*DUP* ↵Johnny Chen2011-04-152-0/+16
| | | | | | | | | instructions (single element or n-element structure to all lanes). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129550 91177308-0d34-0410-b5e6-96231b3b80d8
* Add sanity checkings for Thumb2 Load/Store Register Exclusive family of ↵Johnny Chen2011-04-144-0/+33
| | | | | | operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129531 91177308-0d34-0410-b5e6-96231b3b80d8
* As Dan pointed out, movzbl, movsbl, and friends are nicer than their aliasBill Wendling2011-04-141-26/+26
| | | | | | | (movzx/movsx) because they give more information. Revert that part of the patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129498 91177308-0d34-0410-b5e6-96231b3b80d8
* Have the X86 back-end emit the alias instead of what's being aliased. In mostBill Wendling2011-04-142-70/+70
| | | | | | | cases, it's much nicer and more informative reading the alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129497 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb disassembler did not handle tBRIND (indirect branch) properly.Johnny Chen2011-04-131-0/+3
| | | | | | | rdar://problem/9280370 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129480 91177308-0d34-0410-b5e6-96231b3b80d8
* Check for unallocated instruction encodings when disassembling Thumb Branch ↵Johnny Chen2011-04-132-2/+13
| | | | | | | | | instructions (tBcc and t2Bcc). rdar://problem/9280470 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129471 91177308-0d34-0410-b5e6-96231b3b80d8
* The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.Johnny Chen2011-04-131-0/+10
| | | | | | | rdar://problem/9279440 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129469 91177308-0d34-0410-b5e6-96231b3b80d8
* Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings ↵Johnny Chen2011-04-132-0/+20
| | | | | | | | | as such. rdar://problem/9276651 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129462 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was ↵Johnny Chen2011-04-131-0/+3
| | | | | | | | | not properly handled. rdar://problem/9276427 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129456 91177308-0d34-0410-b5e6-96231b3b80d8
* Add sanity check for Ld/St Dual forms of Thumb2 instructions.Johnny Chen2011-04-122-0/+23
| | | | | | | rdar://problem/9273947 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129411 91177308-0d34-0410-b5e6-96231b3b80d8
* The Thumb2 RFE instructions need to have their second halfword fully specified.Johnny Chen2011-04-121-0/+3
| | | | | | | | | | | In addition, the base register is not rGPR, but GPR with th exception that: if n == 15 then UNPREDICTABLE rdar://problem/9273836 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129391 91177308-0d34-0410-b5e6-96231b3b80d8
* Add bad register checks for Thumb2 Ld/St instructions.Johnny Chen2011-04-121-0/+10
| | | | | | | rdar://problem/9269047 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129387 91177308-0d34-0410-b5e6-96231b3b80d8
* The Thumb2 Ld, St, and Preload instructions with the i12 forms should have ↵Johnny Chen2011-04-121-1/+13
| | | | | | | | | | | its Inst{23} be specified as '1' (add = TRUE). Also add a utility function for Thumb2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129377 91177308-0d34-0410-b5e6-96231b3b80d8
* Print out a debug message when the reglist fails the sanity check for Thumb ↵Johnny Chen2011-04-121-0/+10
| | | | | | Ld/St Multiple. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129365 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the case of a .cfi_rel_offset before any .cfi_def_cfa_offset.Rafael Espindola2011-04-121-0/+41
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129362 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement .cfi_same_value.Rafael Espindola2011-04-121-0/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129361 91177308-0d34-0410-b5e6-96231b3b80d8
* Add one test case (svc).Johnny Chen2011-04-121-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129327 91177308-0d34-0410-b5e6-96231b3b80d8
* Match case for invalid constant error messages and add a newEric Christopher2011-04-121-1/+4
| | | | | | | test for invalid hexadecimals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129326 91177308-0d34-0410-b5e6-96231b3b80d8
* A8.6.16 BJohnny Chen2011-04-121-0/+10
| | | | | | | | | | Encoding T1 (tBcc) if cond == '1110' then UNDEFINED; rdar://problem/9268681 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129325 91177308-0d34-0410-b5e6-96231b3b80d8
* Test for invalid constant expr addition - bad octal constant.Eric Christopher2011-04-121-13/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129323 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb disassembler was erroneously rejecting "blx sp" instruction.Johnny Chen2011-04-111-0/+9
| | | | | | | rdar://problem/9267838 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129320 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement cfi_rel_offsetRafael Espindola2011-04-111-0/+49
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129306 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test for previous commit.Rafael Espindola2011-04-111-0/+46
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129304 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the bug where the immediate shift amount for Thumb logical shift ↵Johnny Chen2011-04-111-0/+6
| | | | | | | | | instructions are incorrectly disassembled. rdar://problem/9266265 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129298 91177308-0d34-0410-b5e6-96231b3b80d8
* Check invalid register encodings for LdFrm/StFrm ARM instructions and flag ↵Johnny Chen2011-04-114-0/+34
| | | | | | | | | them as invalid instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129286 91177308-0d34-0410-b5e6-96231b3b80d8
* fix rdar://8735979 - "int 3" doesn't match to "int3". Unfortunately,Chris Lattner2011-04-091-0/+4
| | | | | | | | InstAlias doesn't allow matching immediate operands, so we have to write C++ code to do this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129223 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't store Twine temporaries, it's not safe.Benjamin Kramer2011-04-091-1/+5
| | | | | | And don't append the name over and over again in the loop. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129210 91177308-0d34-0410-b5e6-96231b3b80d8
* Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.Johnny Chen2011-04-081-0/+3
| | | | | | | | PR9650 rdar://problem/9257565 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129147 91177308-0d34-0410-b5e6-96231b3b80d8
* Sanity check the option operand for DMB/DSB.Johnny Chen2011-04-083-0/+38
| | | | | | | | PR9648 rdar://problem/9257634 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129146 91177308-0d34-0410-b5e6-96231b3b80d8
* MOVi16 and MOVTi16 does not allow pc as the dest register, while MOVi allows it.Johnny Chen2011-04-082-0/+16
| | | | | | | Add tests for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129137 91177308-0d34-0410-b5e6-96231b3b80d8
* Add sanity checking for bad register specifier(s) for the DPFrm instructions.Johnny Chen2011-04-084-0/+50
| | | | | | | Add more test cases to exercise the logical branches related to the above change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129117 91177308-0d34-0410-b5e6-96231b3b80d8
* Update testsRafael Espindola2011-04-0730-71/+71
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129116 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a VEXT test.Johnny Chen2011-04-071-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129111 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for .skip.Rafael Espindola2011-04-071-0/+5
| | | | | | | Patch by Roman Divacky. Fixes PR9361. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129106 91177308-0d34-0410-b5e6-96231b3b80d8
* Add sanity checking for invalid register encodings for signed/unsigned ↵Johnny Chen2011-04-072-0/+17
| | | | | | | | | extend instructions. Add some test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129098 91177308-0d34-0410-b5e6-96231b3b80d8
* Add sanity checking for invalid register encodings for saturating instructions.Johnny Chen2011-04-071-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129096 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some more comments about checkings of invalid register numbers.Johnny Chen2011-04-072-0/+14
| | | | | | | And two test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129090 91177308-0d34-0410-b5e6-96231b3b80d8
* Sanity check MSRi for invalid mask values and reject it as invalid.Johnny Chen2011-04-071-0/+12
| | | | | | | rdar://problem/9246844 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129050 91177308-0d34-0410-b5e6-96231b3b80d8
* The ARM disassembler was not recognizing USADA8 instruction. Need to add ↵Johnny Chen2011-04-071-0/+3
| | | | | | | | | | | checking for register values for USAD8 and USADA8. rdar://problem/9247060 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129047 91177308-0d34-0410-b5e6-96231b3b80d8
* Should also check SMLAD for invalid register values.Johnny Chen2011-04-071-0/+11
| | | | | | | rdar://problem/9246650 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129042 91177308-0d34-0410-b5e6-96231b3b80d8
* A8.6.393Johnny Chen2011-04-061-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM disassembler should reject invalid (type, align) encodings as invalid instructions. So, instead of: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- vst2.32 {d0, d2}, [r3, :256], r3 we now have: Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| ------------------------------------------------------------------------------------------------- mc-input.txt:1:1: warning: invalid instruction encoding 0xb3 0x9 0x3 0xf4 ^ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129033 91177308-0d34-0410-b5e6-96231b3b80d8
* A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP"Johnny Chen2011-04-063-0/+16
| | | | | | | | | | | Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits specified, if coproc == 10 or 11, we should reject the insn as invalid. rdar://problem/9239922 rdar://problem/9239596 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129027 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in the disassembly of VGETLNs8 where the lane index was wrong.Johnny Chen2011-04-061-0/+3
| | | | | | | | | | Also set the encoding bits (for A8.6.303, A8.6.328, A8.6.329) Inst{3-0} = 0b0000, in class NVLaneOp. rdar://problem/9240648 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129015 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a missing opcode (SMLSLDX) to BadRegsMulFrm() function.Johnny Chen2011-04-061-1/+4
| | | | | | | | | | | Add more complete sanity check for LdStFrm instructions where if IBit (Inst{25}) is 1, Inst{4} should be 0. Otherwise, we should reject the insn as invalid. rdar://problem/9239347 rdar://problem/9239467 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128977 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo in the handling of PKHTB opcode, plus add sanity check for ↵Johnny Chen2011-04-051-3/+6
| | | | | | | | | | | illegal register encodings for DisassembleArithMiscFrm(). rdar://problem/9238659 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128958 91177308-0d34-0410-b5e6-96231b3b80d8
* A7.3 register encodingJohnny Chen2011-04-052-1/+11
| | | | | | | | | | | | | | Qd -> bit[12] == 0 Qn -> bit[16] == 0 Qm -> bit[0] == 0 If one of these bits is 1, the instruction is UNDEFINED. rdar://problem/9238399 rdar://problem/9238445 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128949 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM disassembler was erroneously accepting an invalid RSC instruction.Johnny Chen2011-04-051-0/+9
| | | | | | | | | Added checks for regs which should not be 15. rdar://problem/9237734 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128945 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM disassembler was erroneously accepting an invalid LSL instruction.Johnny Chen2011-04-051-0/+9
| | | | | | | | | | For register-controlled shifts, we should check that the encoding constraint Inst{7} = 0 and Inst{4} = 1 is satisfied. rdar://problem/9237693 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128941 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-11-17 18:05:34 +0000