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* Make ARMAsmPrinter generate the correct alignment specifier syntax in ↵Kristof Beyls2013-02-229-302/+302
| | | | | | | | | | | instructions. The Printer will now print instructions with the correct alignment specifier syntax, like vld1.8 {d16}, [r0:64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175884 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips specific standalone assembler addressing mode %hi and %lo.Jack Carter2013-02-212-3/+13
| | | | | | | | | | | | | | The constructs %hi() and %lo() represent the high and low 16 bits of the address. Because the 16 bit offset field of an LW instruction is interpreted as signed, if bit 15 of the low part is 1 then the low part will act as a negative and 1 needs to be added to the high part. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175707 91177308-0d34-0410-b5e6-96231b3b80d8
* ELF symbol table field st_other support, Jack Carter2013-02-203-13/+182
| | | | | | | | | | | | | | | | | | | | | | excluding visibility bits. Mips specific standalone assembler directive "set at". This directive changes the general purpose register that the assembler will use when given the symbolic register name $at. This does not include negative testing. That will come in a future patch. A side affect of this patch recognizes the different GPR register names for temporaries between old abi and new abi so a test case for that is included. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175686 91177308-0d34-0410-b5e6-96231b3b80d8
* ELF symbol table field st_other support, Jack Carter2013-02-191-7/+7
| | | | | | | | | | | | | | excluding visibility bits. Mips (o32 abi) specific e_header setting. EF_MIPS_ABI_O32 needs to be set in the ELF header flags for o32 abi output. Contributer: Reed Kotler git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175569 91177308-0d34-0410-b5e6-96231b3b80d8
* ELF symbol table field st_other support, Jack Carter2013-02-192-2/+18
| | | | | | | | | | | | | | excluding visibility bits. Mips (Mips16) specific e_header setting. EF_MIPS_ARCH_ASE_M16 needs to be set in the ELF header flags for Mips16. Contributer: Reed Kotler git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175566 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add missing 2r instructions.Richard Osborne2013-02-171-0/+9
| | | | | | | These instructions are not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add TSETR instruction.Richard Osborne2013-02-171-0/+3
| | | | | | | This instruction is not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add missing u10 / lu10 instructions.Richard Osborne2013-02-171-0/+12
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175404 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add missing u6 / lu6 instructions.Richard Osborne2013-02-171-0/+36
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175403 91177308-0d34-0410-b5e6-96231b3b80d8
* MCParser: Reject .balign with non-pow2 alignments.Benjamin Kramer2013-02-161-0/+10
| | | | | | | | GNU as rejects them and there are configure scripts in the wild that check if the assembler rejects ".align 3" to determine whether the alignment is in bytes or powers of two. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175360 91177308-0d34-0410-b5e6-96231b3b80d8
* Derive ELF section type from the name in some cases where GNU as doesJoerg Sonnenberger2013-02-161-0/+62
| | | | | | | so. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175327 91177308-0d34-0410-b5e6-96231b3b80d8
* If bundle alignment is enabled, do not add data to a fragment with instructionsDerek Schuff2013-02-151-2/+13
| | | | | | | | | | | | With bundle alignment, instructions all get their own MCFragments (unless they are in a bundle-locked group). For instructions with fixups, this is an MCDataFragment. Emitting actual data (e.g. for .long) attempts to re-use MCDataFragments, which we don't want int this case since it leads to fragments which exceed the bundle size. So, don't reuse them in this case. Also adds a test and fixes some formatting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175316 91177308-0d34-0410-b5e6-96231b3b80d8
* The ARM NEON vector compare instructions take three arguments. However, the Joel Jones2013-02-141-1/+67
| | | | | | | | | | | | | | | assembler should also accept a two arg form, as the docuemntation specifies that the first (destination) register is optional. This patch uses TwoOperandAliasConstraint to add the two argument form. It also fixes an 80-column formatting problem in: test/MC/ARM/neon-bitwise-encoding <rdar://problem/12909419> Clang rejects ARM NEON assembly instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175221 91177308-0d34-0410-b5e6-96231b3b80d8
* death to extra whitespaceKay Tiong Khoo2013-02-141-20/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175200 91177308-0d34-0410-b5e6-96231b3b80d8
* added basic support for Intel ADX instructionsKay Tiong Khoo2013-02-142-0/+36
| | | | | | -feature flag, instructions definitions, test cases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175196 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r15266. This fixes llvm.org/pr15266.Rafael Espindola2013-02-142-20/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175173 91177308-0d34-0410-b5e6-96231b3b80d8
* Make ARMAsmParser accept the correct alignment specifier syntax in instructions.Kristof Beyls2013-02-145-152/+168
| | | | | | | | | | | The parser will now accept instructions with alignment specifiers written like vld1.8 {d16}, [r0:64] , while also still accepting the incorrect syntax vld1.8 {d16}, [r0, :64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175164 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Add support for lexing binary integers with a [bB] suffix.Chad Rosier2013-02-122-6/+20
| | | | | | | | | | | | | | | This is complicated by backward labels (e.g., 0b can be both a backward label and a binary zero). The current implementation assumes [0-9]b is always a label and thus it's possible for 0b and 1b to not be interpreted correctly for ms-style inline assembly. However, this is relatively simple to fix in the inline assembly (i.e., drop the [bB]). This patch also limits backward labels to [0-9]b, so that only 0b and 1b are ambiguous. Part of rdar://12470373 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174983 91177308-0d34-0410-b5e6-96231b3b80d8
* added test cases for r174920 (prefetch disassembly)Kay Tiong Khoo2013-02-121-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174979 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Add support for lexing hexidecimal integers with a [hH] suffix.Chad Rosier2013-02-121-0/+26
| | | | | | Part of rdar://12470373 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174926 91177308-0d34-0410-b5e6-96231b3b80d8
* *fixed disassembly of some i386 system insts with intel syntaxKay Tiong Khoo2013-02-111-0/+13
| | | | | | *added file for test cases for i386 intel syntax git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174900 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: Undo change to how test was runTim Northover2013-02-111-1/+2
| | | | | | This broke on Windows, presumably due to interleaving of output streams. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174873 91177308-0d34-0410-b5e6-96231b3b80d8
* Make use of DiagnosticType to provide better AArch64 diagnostics.Tim Northover2013-02-111-501/+504
| | | | | | | | | This gives a DiagnosticType to all AsmOperands in sight. This replaces all "invalid operand" diagnostics with something more specific. The messages given should still be sufficiently vague that they're not usually actively misleading when LLVM guesses your instruction incorrectly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174871 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add definition of JALR instruction which has two register operands. ↵Akira Hatanaka2013-02-071-0/+8
| | | | | | | | | | Change the original JALR instruction with one register operand to be a pseudo-instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174657 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AArch64 CRC32 instructionsTim Northover2013-02-062-0/+34
| | | | | | | | These instructions are a late addition to the architecture, and may yet end up behind an optional attribute, but for now they're available at all times. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174496 91177308-0d34-0410-b5e6-96231b3b80d8
* Add icache prefetch operations to AArch64Tim Northover2013-02-062-0/+50
| | | | | | | This adds hints to the various "prfm" instructions so that they can affect the instruction cache as well as the data cache. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174495 91177308-0d34-0410-b5e6-96231b3b80d8
* [MC] Bundle alignment: Invalidate relaxed fragmentsDerek Schuff2013-02-051-0/+16
| | | | | | | | | | | | | | | | Currently, when a fragment is relaxed, its size is modified, but its offset is not (it gets laid out as a side effect of checking whether it needs relaxation), then all subsequent fragments are invalidated because their offsets need to change. When bundling is enabled, relaxed fragments need to get laid out again, because the increase in size may push it over a bundle boundary. So instead of only invalidating subsequent fragments, also invalidate the fragment that gets relaxed, which causes it to get laid out again. This patch also fixes some trailing whitespace and fixes the bundling-related debug output of MCFragments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174401 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch that sets the Mips ELF header flag for Jack Carter2013-02-051-0/+8
| | | | | | | | | | MicroMips architectures. Contributer: Zoran Jovanovic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174360 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch that sets the EmitAlias flag in td files Jack Carter2013-02-052-10/+10
| | | | | | | | | | | | | | | and enables the instruction printer to print aliased instructions. Due to usage of RegisterOperands a change in common code (utils/TableGen/AsmWriterEmitter.cpp) is required to get the correct register value if it is a RegisterOperand. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174358 91177308-0d34-0410-b5e6-96231b3b80d8
* Add explicit triples to AArch64 testsTim Northover2013-02-011-2/+2
| | | | | | | | Only Linux is supported at the moment, and other platforms quickly fault. As a result these tests would fail on non-Linux hosts. It may be worth making the tests more generic again as more platforms are supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174170 91177308-0d34-0410-b5e6-96231b3b80d8
* [MC] bundle alignment: prevent padding instructions from crossing bundle ↵Derek Schuff2013-01-312-2/+108
| | | | | | boundaries git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174067 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AArch64 as an experimental target.Tim Northover2013-01-3123-0/+13915
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a special ARM trap encoding for NaCl.Eli Bendersky2013-01-301-4/+11
| | | | | | | | | | More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html Patch by JF Bastien git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173943 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch implements runtime ARM specificJack Carter2013-01-302-1/+13
| | | | | | | | | | setting of ELF header e_flags. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173885 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch implements runtime Mips specificJack Carter2013-01-301-0/+55
| | | | | | | | | | setting of ELF header e_flags. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173884 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch reworks how llvm targets set Jack Carter2013-01-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | and update ELF header e_flags. Currently gathering information such as symbol, section and data is done by collecting it in an MCAssembler object. From MCAssembler and MCAsmLayout objects ELFObjectWriter::WriteObject() forms and streams out the ELF object file. This patch just adds a few members to the MCAssember class to store and access the e_flag settings. It allows for runtime additions to the e_flag by assembler directives. The standalone assembler can get to MCAssembler from getParser().getStreamer().getAssembler(). This patch is the generic infrastructure and will be followed by patches for ARM and Mips for their target specific use. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173882 91177308-0d34-0410-b5e6-96231b3b80d8
* [MC][COFF] Delay handling symbol aliases when writingMichael J. Spencer2013-01-291-0/+11
| | | | | | Fixes PR14447 and PR9034. Patch by Nico Rieck! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173839 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge SSE and AVX shuffle instructions in the comment printer.Craig Topper2013-01-291-0/+225
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173777 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix 256-bit PALIGNR comment decoding to understand that it works on ↵Craig Topper2013-01-281-0/+15
| | | | | | independent 256-bit lanes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173674 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add missing l2rus instructions.Richard Osborne2013-01-271-0/+6
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173634 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add missing l2r instructions.Richard Osborne2013-01-271-0/+12
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173629 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add missing 1r instructions.Richard Osborne2013-01-271-0/+27
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173624 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add missing 0r instructions.Richard Osborne2013-01-271-0/+51
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173623 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Decode PALIGN operands so I don't have to do it in my head.Benjamin Kramer2013-01-261-0/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173572 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction encodings / disassembly support for l4r instructions.Richard Osborne2013-01-251-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
* Now that llvm-dwarfdump supports flags to specify which DWARF section to dump,Eli Bendersky2013-01-256-7/+7
| | | | | | | | | use them in tests that run llvm-dwarfdump. This is in order to make tests as specific as possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173498 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction encodings / disassembly support for l5r instructions.Richard Osborne2013-01-251-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch implements parsing the .wordJack Carter2013-01-251-1/+4
| | | | | | | | | | directive for the Mips assembler. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173407 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction encodings / disassembly support for l6r instructions.Richard Osborne2013-01-231-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction encodings / disassembly support for u10 / lu10 instructions.Richard Osborne2013-01-221-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173204 91177308-0d34-0410-b5e6-96231b3b80d8
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