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* AArch64: remove over-zealous use of CHECK-NEXTTim Northover2013-04-121-38/+38
| | | | | | | | It turns out some platforms (e.g. Windows) lay out their llvm-mc slightly differently with extra newlines; there was no real reason for the test lines to be consecutive, so this relaxes the FileCheck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179375 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace coff-/elf-dump with llvm-readobjNico Rieck2013-04-12135-4678/+4350
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179361 91177308-0d34-0410-b5e6-96231b3b80d8
* Add CLAC/STAC instruction encoding/decoding supportMichael Liao2013-04-112-0/+14
| | | | | | | | | As these two instructions in AVX extension are privileged instructions for special purpose, it's only expected to be used in inlined assembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179266 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Support COFF image-relative MCSymbolRefsNico Rieck2013-04-101-0/+29
| | | | | | | | | | | | | | | | Add support for the COFF relocation types IMAGE_REL_I386_DIR32NB and IMAGE_REL_AMD64_ADDR32NB for 32- and 64-bit respectively. These are similar to normal 4-byte relocations except that they do not include the base address of the image. Image-relative relocations are used for debug information (32-bit) and SEH unwind tables (64-bit). A new MCSymbolRef variant called 'VK_COFF_IMGREL32' is introduced to specify such relocations. For AT&T assembly, this variant can be accessed using the symbol suffix '@imgrel'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179240 91177308-0d34-0410-b5e6-96231b3b80d8
* fixed xsave, xsaveopt, xrstor mnemonics with intel syntax; added test casesKay Tiong Khoo2013-04-102-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179223 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a scheme closer to that of GNU as when deciding the type of aPeter Collingbourne2013-04-101-9/+44
| | | | | | | | symbol with multiple .type declarations. Differential Revision: http://llvm-reviews.chandlerc.com/D607 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179184 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Make "SMC" instructions conditional on new TrustZone architecture feature.Tim Northover2013-04-106-18/+82
| | | | | | | | | | | | These instructions aren't universally available, but depend on a specific extension to the normal ARM architecture (rather than, say, v6/v7/...) so a new feature is appropriate. This also enables the feature by default on A-class cores which usually have these extensions, to avoid breaking existing code and act as a sensible default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179171 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Add support for numeric displacement expressions in bracketedChad Rosier2013-04-051-1/+38
| | | | | | | | | | | | | | | | | | | | | | | memory operands. Essentially, this layers an infix calculator on top of the parsing state machine. The scale on the index register is still expected to be an immediate __asm mov eax, [eax + ebx*4] and will not work with more complex expressions. For example, __asm mov eax, [eax + ebx*(2*2)] The plus and minus binary operators assume the numeric value of a register is zero so as to not change the displacement. Register operands should never be an operand for a multiply or divide operation; the scale*indexreg expression is always replaced with a zero on the operand stack to prevent such a case. rdar://13521380 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178881 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add bru instruction.Richard Osborne2013-04-041-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178783 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] The RRegs register class is a superset of GRRegs.Richard Osborne2013-04-041-0/+48
| | | | | | | | | | At the time when the XCore backend was added there were some issues with with overlapping register classes but these all seem to be fixed now. Describing the register classes correctly allow us to get rid of a codegen only instruction (LDAWSP_lru6_RRegs) and it means we can disassemble ru6 instructions that use registers above r11. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178782 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the "mips endian" for r_info.Rafael Espindola2013-04-031-1/+1
| | | | | | | | Normally r_info is just a 32 of 64 bit number matching the endian of the rest of the file. Unfortunately, mips 64 bit little endian is special: The top 32 bits are a little endian number and the following 32 are a big endian one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178694 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Check disassembly of the st8 instruction.Richard Osborne2013-04-031-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178689 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Update disassembler test to improve coverage of the instructions.Richard Osborne2013-04-031-6/+6
| | | | | | | Previously some instructions were unintentionally covered twice and others were not covered at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178688 91177308-0d34-0410-b5e6-96231b3b80d8
* Implements low-level object file format specific output for COFF andEric Christopher2013-04-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ELF with support for: - File headers - Section headers + data - Relocations - Symbols - Unwind data (only COFF/Win64) The output format follows a few rules: - Values are almost always output one per line (as elf-dump/coff-dump already do). - Many values are translated to something readable (like enum names), with the raw value in parentheses. - Hex numbers are output in uppercase, prefixed with "0x". - Flags are sorted alphabetically. - Lists and groups are always delimited. Example output: ---------- snip ---------- Sections [ Section { Index: 1 Name: .text (5) Type: SHT_PROGBITS (0x1) Flags [ (0x6) SHF_ALLOC (0x2) SHF_EXECINSTR (0x4) ] Address: 0x0 Offset: 0x40 Size: 33 Link: 0 Info: 0 AddressAlignment: 16 EntrySize: 0 Relocations [ 0x6 R_386_32 .rodata.str1.1 0x0 0xB R_386_PC32 puts 0x0 0x12 R_386_32 .rodata.str1.1 0x0 0x17 R_386_PC32 puts 0x0 ] SectionData ( 0000: 83EC04C7 04240000 0000E8FC FFFFFFC7 |.....$..........| 0010: 04240600 0000E8FC FFFFFF31 C083C404 |.$.........1....| 0020: C3 |.| ) } ] ---------- snip ---------- Relocations and symbols can be output standalone or together with the section header as displayed in the example. This feature set supports all tests in test/MC/COFF and test/MC/ELF (and I suspect all additional tests using elf-dump), making elf-dump and coff-dump deprecated. Patch by Nico Rieck! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178679 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: implement ETMv4 trace system registers.Tim Northover2013-04-033-0/+1658
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178637 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the fde encoding used by mips to match gas.Rafael Espindola2013-04-033-108/+156
| | | | | | | | | | | | | This finally fixes the encoding. The patch also * Removes eh-frame.ll. It was an unnecessary .ll to .o test that was checking the wrong value. * Merge fde-reloc.s and eh-frame.s into a single test, since the only difference was the run lines. * Don't blindly test the content of the entire .eh_frame section. It makes it hard to anyone actually fixing a bug and hitting a difference in a binary blob. Instead, use a CHECK for each field and document what is being checked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178615 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips direct object exception handling regressionJack Carter2013-04-012-0/+67
| | | | | | | | | | | | | | | | | | | Revision 177141 caused a regression in all but mips64 little endian. That is because none of the other Mips targets had test cases checking the contents of the .eh_frame section. This patch fixes both the llvm code and adds an assembler test case to include the current 4 flavors. The test cases unfortunately rely on llvm-objdump. A preferable method would be to use a pretty printer output such as what readelf -wf <elf_file> would give. I also changed the name of the test case to correct a typo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178506 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips Assembler] Add support for OR macro with imediate opperandJack Carter2013-03-281-0/+2
| | | | | | | | | | | Mips assembler supports macros that allows the OR instruction to have an immediate parameter. This patch adds an instruction alias that converts this macro into a Mips ORI instruction. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178316 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support of RDSEED defined in AVX2 extensionMichael Liao2013-03-281-0/+49
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178314 91177308-0d34-0410-b5e6-96231b3b80d8
* [Mips Assembler] Add alias definitions for jalJack Carter2013-03-281-1/+15
| | | | | | | | | | | | | Mips assembler allows following to be used as aliased instructions: jal $rs for jalr $rs jal $rd,$rd for jalr $rd,$rs This patch provides alias definitions in td files and test cases to show the usage. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178304 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when ↵Gordon Keiser2013-03-281-0/+3
| | | | | | | | | | the upper bit is set. They should always be zero-extended, not sign extended. Added test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178275 91177308-0d34-0410-b5e6-96231b3b80d8
* Move test since it depends on the X86 backend.Rafael Espindola2013-03-281-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178249 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: implement GICv3 system registersTim Northover2013-03-283-0/+506
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178236 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Updated ELF relocation test for .eh_frame section"Michael Gottesman2013-03-281-26/+4
| | | | | | | | This reverts commit c8d65364223a04b179958a50a4bf0f89b21dd7d2. This broke a bunch of the buildbots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178222 91177308-0d34-0410-b5e6-96231b3b80d8
* Updated ELF relocation test for .eh_frame sectionJack Carter2013-03-271-4/+26
| | | | | | | | | Made sure we were looking a correct section Added Mips32/64 as an extra check Updated llvm-objdump to generate symbolic info for Mips relocations git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178190 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Add support of imm displacement before bracketed memoryChad Rosier2013-03-271-0/+20
| | | | | | | | | | | | | | | expression. Specifically, this syntax: ImmDisp [ BaseReg + Scale*IndexReg + Disp ] We don't currently support: ImmDisp [ Symbol ] rdar://13518671 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178186 91177308-0d34-0410-b5e6-96231b3b80d8
* test file name change to correct typoJack Carter2013-03-271-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178174 91177308-0d34-0410-b5e6-96231b3b80d8
* Patch by Gordon Keiser!Joe Abbey2013-03-261-0/+2
| | | | | | | | | | | | If PC or SP is the destination, the disassembler erroneously failed with the invalid encoding, despite the manual saying that both are fine. This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a postindexed load, where the offset 0xc is applied to SP after the load occurs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178017 91177308-0d34-0410-b5e6-96231b3b80d8
* x86 -- add the XTEST instructionDave Zarzycki2013-03-251-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177888 91177308-0d34-0410-b5e6-96231b3b80d8
* x86 -- disassemble the REP/REPNE prefix when neededDave Zarzycki2013-03-251-0/+15
| | | | | | This fixes Apple bug: 13493622 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177887 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the invalid opcode for Mips branch instructions in the assemblerJack Carter2013-03-221-12/+12
| | | | | | | | | | | | | | | | | | For mips a branch an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. Previously, the code generator did not perform the shift of the immediate branch offset which resulted in wrong instruction opcode. This patch fixes the issue. Contributor: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177687 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch that enables the Mips assembler to use symbols for offset for ↵Jack Carter2013-03-221-0/+22
| | | | | | | | | | | | | | | instructions This patch uses the generated instruction info tables to identify memory/load store instructions. After successful matching and based on the operand type and size, it generates additional instructions to the output. Contributor: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177685 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch enables the Mips .set directive to define aliasesJack Carter2013-03-211-0/+6
| | | | | | | | | | | | | | | | | | | The .set directive in the Mips the assembler can be used to set the value of a symbol to an expression. This changes the symbol's value and type to conform to the expression's. Syntax: .set symbol, expression This patch implements the parsing of the above syntax and enables the parser to use defined symbols when parsing operands. Contributor: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177667 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix pr13145 - Naming a function like a register name confuses the asm parser.Chad Rosier2013-03-191-0/+5
| | | | | | | Patch by Stepan Dyatkovskiy <stpworld@narod.ru> rdar://13457826 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177463 91177308-0d34-0410-b5e6-96231b3b80d8
* Post process ADC/SBB and use a shorter encoding if they use a sign extended ↵Craig Topper2013-03-181-0/+14
| | | | | | immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177243 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor some duplicated code into helper functions.Craig Topper2013-03-181-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177242 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the FDE encoding to be relative on ELF.Rafael Espindola2013-03-151-0/+11
| | | | | | | | | | | | This is a very late complement to r130637 which fixed this on x86_64. Fixes pr15448. Since it looks like that every elf architecture uses this encoding when using cfi, make it the default for elf. Just exclude mips64el. It has a lovely .ll -> .o test (ef_frame.ll) that tests that nothing changes in the binary content of the .eh_frame produced by llc. Oblige it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177141 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in the calculation of the VEX.B bit for FMA4 rr with the VEX.W bit ↵Craig Topper2013-03-141-0/+4
| | | | | | set. The VEX.B was being calculated from the wrong operand. Fixes at least some portion of PR14185. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177014 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixes disassembler crashes on 2013 Haswell RTM instructions.Kevin Enderby2013-03-111-0/+9
| | | | | | | rdar://13318048 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176828 91177308-0d34-0410-b5e6-96231b3b80d8
* We need a shndx if the number of sections breaks SHN_LORESERVE. This conditionNick Lewycky2013-03-091-0/+65281
| | | | | | | for choosing to emit a shndx was simply testing the wrong variable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176762 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixes a test by replacing .align by .p2align and setting triples explicitly.Eli Bendersky2013-03-051-2/+5
| | | | | | | | Patch by David Sehr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176502 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test that .align directives on capable processors use long NOPs.David Sehr2013-03-051-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176490 91177308-0d34-0410-b5e6-96231b3b80d8
* The current X86 NOP padding uses one long NOP followed by the remainder inDavid Sehr2013-03-051-0/+27
| | | | | | | | | | | | one-byte NOPs. If the processor actually executes those NOPs, as it sometimes does with aligned bundling, this can have a performance impact. From my micro-benchmarks run on my one machine, a 15-byte NOP followed by twelve one-byte NOPs is about 20% worse than a 15 followed by a 12. This patch changes NOP emission to emit as many 15-byte (the maximum) as possible followed by at most one shorter NOP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176464 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite a test to check actual output rather than intermediate implementationEli Bendersky2013-03-011-6/+6
| | | | | | | | | | | | | | | | | | | | detail. The was this test was written, it was relying on an implementation detail (fixups) and hence was very brittle (relying, among other things, on the exact ordering of statistics printed by MC). The test was rewritten to check a more observable output difference. While it doesn't cover 100% of the things the original test covered, it's a good practice to write regression tests this way. If we want to check that internal details and invariants hold, such tests should be expressed as unit tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176377 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: remove post-encoder method from FCMP (immediate) instructions.Tim Northover2013-02-281-0/+8
| | | | | | | | The work done by the post-encoder (setting architecturally unused bits to 0 as required) can be done by the existing operand that covers the "#0.0". This removes at least one use of the discouraged PostEncoderMethod uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176261 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: permit full range of valid ADR immediates.Tim Northover2013-02-271-0/+4
| | | | | | | | | This fixes an issue where trying to assemlbe valid ADR instructions would cause LLVM to hit a failed assertion. Patch by Keith Walker. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176189 91177308-0d34-0410-b5e6-96231b3b80d8
* AsmParser: More generic support for integer type suffices.Jim Grosbach2013-02-261-0/+6
| | | | | | | | | | For integer constants, allow 'L', 'UL' as well as 'ULL' and 'LL'. This provides better support for shared headers between .s and .c files that define bunches of constant values. rdar://9321056 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176118 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Add support for the pushad/popad mnemonics.Chad Rosier2013-02-251-0/+13
| | | | | | rdar://13254235 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176036 91177308-0d34-0410-b5e6-96231b3b80d8
* 'Hexadecimal' has two 'a's and only one 'i'.Matt Beaumont-Gay2013-02-251-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176031 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Convenience aliases for 'srs*' instructions.Jim Grosbach2013-02-232-0/+69
| | | | | | | | Handle an implied 'sp' operand. rdar://11466783 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175940 91177308-0d34-0410-b5e6-96231b3b80d8
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