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* Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInstKevin Enderby2012-11-291-0/+11
| | | | | | | which would then cause an assert when printed. rdar://11437956 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168960 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix initial frame state on powerpc64.Ulrich Weigand2012-11-281-0/+41
| | | | | | | | | | The createPPCMCAsmInfo routine used PPC::R1 as the initial frame pointer register, but on PPC64 the 32-bit R1 register does not have a corresponding DWARF number, causing invalid CIE initial frame state to be emitted. Fix by using PPC::X1 instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168799 91177308-0d34-0410-b5e6-96231b3b80d8
* The section is .debug_line.Eric Christopher2012-11-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168666 91177308-0d34-0410-b5e6-96231b3b80d8
* Make this test less sensitive.Eli Bendersky2012-11-261-4/+4
| | | | | | | | It currently assumes register numbering and any harmless change in the X86 register naming makes it fail. It's enough to match the register names. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168632 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for .cfi_register now that it is easy to extent the representationRafael Espindola2012-11-251-0/+42
| | | | | | | to support it. Original patch with the parsing and plumbing by the PaX team and Roman Divacky. I added the bits in MCDwarf.cpp and the test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168565 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement .cfi_undefined. Based on a patch from PaX team, updated byRafael Espindola2012-11-231-0/+41
| | | | | | Roman Divacky. I just added the testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168520 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips direct object xgot supportJack Carter2012-11-211-0/+42
| | | | | | | | | | | | | | | | This patch provides support for the MIPS relocations: *) R_MIPS_GOT_HI16 *) R_MIPS_GOT_LO16 *) R_MIPS_CALL_HI16 *) R_MIPS_CALL_LO16 These are used for large GOT instruction sequences. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168471 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch is in preparation for adding medium code model support to theBill Schmidt2012-11-141-1/+1
| | | | | | | | | | | | | | | | PPC64 target. The five tests modified herein test code generation that is sensitive to the code model selected. So I've added -code-model=small to the RUN commands for each. Since small code model is the default, this has no effect for now; but this prepares us for eventually changing the default to medium code model for PPC64. Test changes verified with small and medium code model as default on powerpc64-unknown-linux-gnu. All tests continue to pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167999 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove DOS line endings.Jakub Staszak2012-11-144-316/+316
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167968 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches.Jim Grosbach2012-11-141-1/+1
| | | | | | | | | | When an instruction as written requires 32-bit mode and we're assembling in 64-bit mode, or vice-versa, issue a more specific diagnostic about what's wrong. rdar://12700702 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167937 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit relocations from .debug_aranges to .debug_info for asm filesAlexey Samsonov2012-11-141-2/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167926 91177308-0d34-0410-b5e6-96231b3b80d8
* [MC][COFF] Emit weak symbols to the correct section. Patch by Dmitry Puzirev!Michael J. Spencer2012-11-131-0/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167877 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test case to verify correct relocs being generated forUlrich Weigand2012-11-131-0/+28
| | | | | | | TLS symbols on PowerPC using the integrated assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167875 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert an improper CodeGen test to a MC test.Evan Cheng2012-11-101-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167663 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support of RTM from TSX extensionMichael Liao2012-11-081-0/+13
| | | | | | | | | | - Add RTM code generation support throught 3 X86 intrinsics: xbegin()/xend() to start/end a transaction region, and xabort() to abort a tranaction region git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for PR14264 cause by commit r167237 which did not take into account aKevin Enderby2012-11-051-0/+17
| | | | | | | | | possible buffer change with a .macro directive. rdar://12637628 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167408 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Stop reserving register AT and use register scavenger when a scratchAkira Hatanaka2012-11-031-2/+2
| | | | | | | | register is needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167341 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix disassembler test cases.Akira Hatanaka2012-11-024-24/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167326 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for generating dwarf debugging info with assembly filesKevin Enderby2012-11-011-0/+22
| | | | | | | | | | | | run through the 'C' preprocessor. That is pick up the file name and line numbers from the cpp hash file line comments for the dwarf file and line numbers tables. rdar://9275556 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167237 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Simple example parser for MC assembly markup.Jim Grosbach2012-10-312-0/+18
| | | | | | Nothing fancy, just a simple demonstration parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167181 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Better disassembly for pc-relative LDR.Jim Grosbach2012-10-305-7/+9
| | | | | | | | | When the operand is a plain immediate rather than a label, print it as [pc, #imm] like we do for the Thumb2 wide encoding variant. rdar://12154503 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166991 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch targetKevin Enderby2012-10-292-0/+15
| | | | | | | | is 24 bits not 20 and the decoding needed to correctly handle converting the J1 and J2 bits to their I1 and I2 values to reconstruct the displacement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166982 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Add support for the [] operator. Essentially, [expr1][expr2] isChad Rosier2012-10-291-0/+50
| | | | | | | equivalent to [expr1 + expr2]. See test cases for more examples. rdar://12470392 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166949 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial TOC support for PowerPC64 object creationAdhemerval Zanella2012-10-252-0/+71
| | | | | | | | | | | | | | | | This patch adds initial PPC64 TOC MC object creation using the small mcmodel (a single 64K TOC) adding the some TOC relocations (R_PPC64_TOC, R_PPC64_TOC16, and R_PPC64_TOC16DS). The addition of 'undefinedExplicitRelSym' hook on 'MCELFObjectTargetWriter' is meant to avoid the creation of an unreferenced ".TOC." symbol (used in the .odp creation) as well to set the R_PPC64_TOC relocation target as the temporary ".TOC." symbol. On PPC64 ABI, the R_PPC64_TOC relocation should not point to any symbol. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166677 91177308-0d34-0410-b5e6-96231b3b80d8
* Tell llvm-mc we're using intel syntax, so we don't have to use directives.Chad Rosier2012-10-241-8/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166640 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Add back-end test case for r166632. Make sure we emit theChad Rosier2012-10-241-0/+12
| | | | | | | | correct .s output as well as get the correct encoding by the integrated assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166638 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for annotated disassembly output for X86 and arm.Kevin Enderby2012-10-222-0/+13
| | | | | | | | | | | | Per the October 12, 2012 Proposal for annotated disassembly output sent out by Jim Grosbach this set of changes implements this for X86 and arm. The llvm-mc tool now has a -mdis option to produced the marked up disassembly and a couple of small example test cases have been added. rdar://11764962 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166445 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Depending on the local semantics of .align this test can also emit a ↵Benjamin Kramer2012-10-131-1/+1
| | | | | | nopl instead of nopw. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165880 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Disable long nops for all cpus prior to pentiumpro/i686.Benjamin Kramer2012-10-131-2/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165878 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test cases for correct parsing of register names in 32- and 64-bit modes.David Chisnall2012-10-112-0/+141
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165713 91177308-0d34-0410-b5e6-96231b3b80d8
* Expose move to/from coprocessor instructions in MIPS64 mode.David Chisnall2012-10-111-0/+37
| | | | | | | | | | | | | Note: [D]M{T,F}CP2 is just a recommended encoding. Vendors often provide a custom CP2 that interprets instructions differently and may wish to add their own instructions that use this opcode. We should ensure that this is easy to do. I will probably add a 'has custom CP{0-3}' subtarget flag to make this easy: We want to avoid the GCC situation where every MIPS vendor makes a custom fork that breaks every other MIPS CPU and so can't be merged upstream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165711 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for r165480.Craig Topper2012-10-101-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165594 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial assembler implementation of Mips load address macroJack Carter2012-10-091-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides initial implementation of load address macro instruction for Mips. We have implemented two kinds of expansions with their variations depending on the size of immediate operand: 1) load address with immediate value directly: * la d,j => addiu d,$zero,j (for -32768 <= j <= 65535) * la d,j => lui d,hi16(j) ori d,d,lo16(j) (for any other 32 bit value of j) 2) load load address with register offset value * la d,j(s) => addiu d,s,j (for -32768 <= j <= 65535) * la d,j(s) => lui d,hi16(j) (for any other 32 bit value of j) ori d,d,lo16(j) addu d,d,s This patch does not cover the case when the address is loaded from the value of the label or function. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165561 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding support for instructions mfc0, mfc2, mtc0, mtc2Jack Carter2012-10-061-0/+16
| | | | | | | | | move from and to coprocessors 0 and 2. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165351 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement methods that enable expansion of load immediate Jack Carter2012-10-041-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | macro instruction (li) in the assembler. We have identified three possible expansions depending on the size of immediate operand: 1) for 0 ≤ j ≤ 65535. li d,j => ori d,$zero,j 2) for −32768 ≤ j < 0. li d,j => addiu d,$zero,j 3) for any other value of j that is representable as a 32-bit integer. li d,j => lui d,hi16(j) ori d,d,lo16(j) All of the above have been implemented in ths patch. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165199 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch is a partial implementation of mips .set assembler directive. ↵Jack Carter2012-10-041-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Directive is defined as follows: .set option The patch implements following options at - lets the assembler use the $at register for macros, but generates warnings if the source program uses $at noat - let source programs use $at without issuingwarnings. noreorder - prevents the assembler from reordering machine language instructions. nomacro - causes the assembler to print a warning whenever an assembler operation generates more than one machine language instruction. macro - lets the assembler generate multiple machine instructions from a single assembler instruction reorder - lets the assembler reorder machine language instructions to improve performance The above variants are parsed and their boolean values set or unset. The code to actually use them will come later. Following options are not implemented yet: nomips16 nomicromips move nomove Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165194 91177308-0d34-0410-b5e6-96231b3b80d8
* MachO: direct-to-object attribute for data-in-code markers.Jim Grosbach2012-10-012-1/+109
| | | | | | | | | | The target backend can support data-in-code load commands even when the assembler doesn't, or vice-versa. Allow targets to opt-in for direct-to-object. PR13973. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164974 91177308-0d34-0410-b5e6-96231b3b80d8
* X86_32: Large Symbol+Offset relocations.Jim Grosbach2012-09-261-0/+36
| | | | | | | | | | If the offset is more than 24-bits, it won't fit in a scattered relocation offset field, so we fall back to using a non-scattered relocation. rdar://12358909 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164724 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Darwin BL/BLX relocations to out-of-range symbols.Jim Grosbach2012-09-251-0/+43
| | | | | | | | | | | When a BL/BLX references a symbol in the same translation unit that is out of range, use an external relocation. The linker will use this to generate a branch island rather than a direct reference, allowing the relocation to resolve correctly. rdar://12359919 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164615 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: 'add Rd, pc, #imm' is an alias for 'adr Rd, #imm'.Jim Grosbach2012-09-251-0/+4
| | | | | | rdar://9795790 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164577 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit dtors into proper section while compiling in vcpp-compatible mode.Anton Korobeynikov2012-09-231-6/+17
| | | | | | | Patch by Kai! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164476 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix edge cases of ARM shift operands in arith instructions.Tim Northover2012-09-222-0/+88
| | | | | | | | | As before with load instructions, oddities like "asr #32", "rrx" could be printed incorrectly. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164456 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the handling of edge cases in ARM shifted operands.Tim Northover2012-09-222-0/+116
| | | | | | | | | This patch fixes load/store instructions to handle less common cases like "asr #32", "rrx" properly throughout the MC layer. Patch by Chris Lidbury. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164455 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for macro parameters/arguments delimited by spaces,Preston Gurd2012-09-192-8/+50
| | | | | | | | | | | | to improve compatibility with GNU as. Based on a patch by PaX Team. Fixed assertion failures on non-Darwin and added additional test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164248 91177308-0d34-0410-b5e6-96231b3b80d8
* Support default parameters/arguments for assembler macros.Preston Gurd2012-09-191-2/+10
| | | | | | | | | | This patch is based on the one by PaX Team. Patch by Andy Zhang! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164246 91177308-0d34-0410-b5e6-96231b3b80d8
* Enhance unmatched '.endr' directive error message in assembler.Preston Gurd2012-09-191-1/+1
| | | | | | | | | | The directive can be matched with directives other than '.rept' Patch by Andy Zhang! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164245 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/MC/X86/x86_nop.s: Make sure -arch=x86 when -mcpu=geode.NAKAMURA Takumi2012-09-191-1/+1
| | | | | | -mcpu doesn't infer -arch. Consider non-x86 host. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164185 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test for r164132.Roman Divacky2012-09-181-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164134 91177308-0d34-0410-b5e6-96231b3b80d8
* Assembler: Darwin variables defined via .set are no-dead-strip.Jim Grosbach2012-09-131-0/+158
| | | | | | | | For gas compatibility. rdar://12219394 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163854 91177308-0d34-0410-b5e6-96231b3b80d8
* Add newline.Chad Rosier2012-09-101-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163565 91177308-0d34-0410-b5e6-96231b3b80d8
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