aboutsummaryrefslogtreecommitdiffstats
path: root/test/MC
Commit message (Collapse)AuthorAgeFilesLines
* Thumb instructions which have reglist operands at the end and predicate operandsJohnny Chen2010-04-211-2/+5
| | | | | | | | | before reglist were not properly handled with respect to IT Block. Fix that by creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those instructions for disassembly. Add a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101974 91177308-0d34-0410-b5e6-96231b3b80d8
* When doing Thumb disassembly, there's no need to consider ↵Johnny Chen2010-04-201-0/+3
| | | | | | | | | t2ADDrSPi12/t2SUBrSPi12, as their generic counterparts t2ADDri12/t2SUBri12 should suffice. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101929 91177308-0d34-0410-b5e6-96231b3b80d8
* For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if ↵Johnny Chen2010-04-201-0/+3
| | | | | | | | | | | Rn(Inst{19-16})=='1111', transform the Opcode to the corresponding t2LDR*pci counterpart. Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101915 91177308-0d34-0410-b5e6-96231b3b80d8
* According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1Johnny Chen2010-04-191-0/+3
| | | | | | | | | | | Pseudocode details of conditional, Condition bits '111x' indicate the instruction is always executed. That is, '1111' is a leagl condition field value, which is now mapped to ARMCC::AL. Also add a test case for condition field '1111'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101817 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM disassembler did not react to recent changes to the NEON instruction table.Johnny Chen2010-04-191-0/+4
| | | | | | | VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101784 91177308-0d34-0410-b5e6-96231b3b80d8
* teach the x86 asm parser how to handle segment prefixesChris Lattner2010-04-171-1/+3
| | | | | | | in memory operands. rdar://7874844 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101661 91177308-0d34-0410-b5e6-96231b3b80d8
* testcase for r101538, patch by Nico Schmidt!Chris Lattner2010-04-171-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101642 91177308-0d34-0410-b5e6-96231b3b80d8
* a bunch of ssse3 instructions are misencoded to think they have an Chris Lattner2010-04-171-0/+7
| | | | | | | i8 field when they really do not. This fixes rdar://7840289 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101629 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor change to make the test case comply with Vd<0> == '0' when Q == '1'.Johnny Chen2010-04-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101559 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a bug in DisassembleN1RegModImmFrm() where a break stmt was missing for aJohnny Chen2010-04-161-0/+3
| | | | | | | | | | | case. Also, the 0xFF hex literal involved in the shift for ESize64 should be suffixed "ul" to preserve the shift result. Implemented printHex*ImmOperand() by copying from ARMAsmPrinter.cpp and added a test case for DisassembleN1RegModImmFrm()/printHex64ImmOperand(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101557 91177308-0d34-0410-b5e6-96231b3b80d8
* In the same spirit of r101524, which removed the assert() from ↵Johnny Chen2010-04-161-0/+3
| | | | | | | | | printAddrMode2OffsetOperand(), this patch removes the assert() from printAddrMode3OffsetOperand() and adds a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101529 91177308-0d34-0410-b5e6-96231b3b80d8
* Multiclass LdStCop was using pre-UAL syntax LDC<c>L for the L fragment. ChangedJohnny Chen2010-04-161-0/+3
| | | | | | | | | | to the UAL syntax of LDCL<c>, instead. Add a test case for this change which also tests the removal of assert() from printAddrMode2OffsetOperand(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101527 91177308-0d34-0410-b5e6-96231b3b80d8
* Added another test case for am3offset operand, testing Rn, #+/-imm8.Johnny Chen2010-04-151-0/+3
| | | | | | | Previous checkin tested Rn, #+/-Rm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101418 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a bug in ARM disassembly where LDRSBT should have am3offset operand, notJohnny Chen2010-04-151-0/+3
| | | | | | | am2offset. Modified the instruction table entry and added a new test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101415 91177308-0d34-0410-b5e6-96231b3b80d8
* tests: MC/Disassembler tests depend on ARM support being compiler in.Daniel Dunbar2010-04-151-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101337 91177308-0d34-0410-b5e6-96231b3b80d8
* implement mc asmparser support for '.', which gets theChris Lattner2010-04-141-0/+11
| | | | | | | | | | | | | | | | | | | | | current PC. rdar://7834775 We now produce an identical .o file compared to the cctools assembler for something like this: _f0: L0: jmp L1 .long . - L0 L1: jmp A .long . - L1 .zerofill __DATA,_bss,A,0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101227 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a crasher in arm disassembler within ARMInstPrinter.cpp after callingJohnny Chen2010-04-121-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM_AM::getSoImmVal(V) with a legitimate so_imm value: #245 rotate right by 2. Introduce ARM_AM::getSOImmValOneOrNoRotate(unsigned Arg) which is called from ARMInstPrinter.cpp's printSOImm() function, replacing ARM_AM::getSOImmVal(V). [12:44:43] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $ gdb Debug/bin/llvm-mc GNU gdb 6.3.50-20050815 (Apple version gdb-1346) (Fri Sep 18 20:40:51 UTC 2009) Copyright 2004 Free Software Foundation, Inc. GDB is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. Type "show copying" to see the conditions. There is absolutely no warranty for GDB. Type "show warranty" for details. This GDB was configured as "x86_64-apple-darwin"...Reading symbols for shared libraries ... done (gdb) set args -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble (gdb) r Starting program: /Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc -triple=arm-apple-darwin9 -debug-only=arm-disassembler --disassemble Reading symbols for shared libraries ++. done 0xf5 0x71 0xf0 0x53 Opcode=201 Name=MVNi Format=ARM_FORMAT_DPFRM(4) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 0: 1: 0: 1| 0: 0: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 1: 1| 0: 0: 0: 1| 1: 1: 1: 1| 0: 1: 0: 1| ------------------------------------------------------------------------------------------------- mvnpls r7, Assertion failed: (V != -1 && "Not a valid so_imm value!"), function printSOImm, file ARMInstPrinter.cpp, line 229. Program received signal SIGABRT, Aborted. 0x00007fff88c65886 in __kill () (gdb) bt #0 0x00007fff88c65886 in __kill () #1 0x00007fff88d05eae in abort () #2 0x00007fff88cf2ef0 in __assert_rtn () #3 0x000000010020e422 in printSOImm (O=@0x1010bdf80, V=-1, VerboseAsm=false, MAI=0x1020106d0) at ARMInstPrinter.cpp:229 #4 0x000000010020e5fe in llvm::ARMInstPrinter::printSOImmOperand (this=0x1020107e0, MI=0x7fff5fbfee70, OpNum=1, O=@0x1010bdf80) at ARMInstPrinter.cpp:254 #5 0x00000001001ffbc0 in llvm::ARMInstPrinter::printInstruction (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMGenAsmWriter.inc:3236 #6 0x000000010020c27c in llvm::ARMInstPrinter::printInst (this=0x1020107e0, MI=0x7fff5fbfee70, O=@0x1010bdf80) at ARMInstPrinter.cpp:182 #7 0x000000010003cbff in PrintInsts (DisAsm=@0x10200f4e0, Printer=@0x1020107e0, Bytes=@0x7fff5fbff060, SM=@0x7fff5fbff078) at Disassembler.cpp:65 #8 0x000000010003c8b4 in llvm::Disassembler::disassemble (T=@0x1010c13c0, Triple=@0x1010b6798, Buffer=@0x102010690) at Disassembler.cpp:153 #9 0x000000010004095c in DisassembleInput (ProgName=0x7fff5fbff3f0 "/Volumes/data/llvm/git/trunk/Debug/bin/llvm-mc") at llvm-mc.cpp:347 #10 0x000000010003eefb in main (argc=4, argv=0x7fff5fbff298) at llvm-mc.cpp:374 (gdb) q The program is running. Exit anyway? (y or n) y [13:36:26] johnny:/Volumes/data/llvm/git/trunk (local-trunk) $ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101053 91177308-0d34-0410-b5e6-96231b3b80d8
* unXFAIL, arm disassembler was reenabled.Benjamin Kramer2010-04-073-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100692 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverting 100265 to try to get buildbots green again. Lots of self-hosting ↵Evan Cheng2010-04-053-0/+3
| | | | | | buildbots started complaining since this commit. Also xfail ARM disassembly tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100378 91177308-0d34-0410-b5e6-96231b3b80d8
* Second try of initial ARM/Thumb disassembler check-in. It consists of a tablgenJohnny Chen2010-04-023-0/+184
| | | | | | | | | | | backend (ARMDecoderEmitter) which emits the decoder functions for ARM and Thumb, and the disassembler core which invokes the decoder function and builds up the MCInst based on the decoded Opcode. Reviewed by Chris Latter and Bob Wilson. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100233 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/Mach-O/x86_64: Support @GOTPCREL on symbols, even for non-PCrel relocations!Daniel Dunbar2010-03-291-18/+53
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99853 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply Kevin's change 94440, now that Chris has fixed the limitation onBob Wilson2010-03-252-0/+84
| | | | | | | opcode values fitting in one byte (svn r99494). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99514 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Fix refacto in MCExpr evaluation, I mistakenly replaced a fragment ↵Daniel Dunbar2010-03-251-24/+166
| | | | | | | | address with a symbol address. - This fixes the integrated-as nightly test regressions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99466 91177308-0d34-0410-b5e6-96231b3b80d8
* Speculatively revert this to see if it fixes buildbot failures.Bob Wilson2010-03-242-84/+0
| | | | | | | | | | | | | --- Reverse-merging r99440 into '.': U test/MC/AsmParser/X86/x86_32-bit_cat.s U test/MC/AsmParser/X86/x86_32-encoding.s U include/llvm/IntrinsicsX86.td U include/llvm/CodeGen/SelectionDAGNodes.h U lib/Target/X86/X86InstrSSE.td U lib/Target/X86/X86ISelLowering.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99450 91177308-0d34-0410-b5e6-96231b3b80d8
* Added the Advanced Encryption Standard (AES) Instructions.Kevin Enderby2010-03-242-0/+84
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99440 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed the SS42AI template for the SSE 4.2 instructions with TA prefix so it doesKevin Enderby2010-03-241-0/+8
| | | | | | | | | not get an "Unknown immediate size" assert failure when used. All instructions of this form have an 8-bit immediate. Also added a test case of an example instruction that is of this form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99435 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/Mach-O: Remove Darwin host specific tests, we don't need them anymore.Daniel Dunbar2010-03-203-758/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99100 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/Mach-O: Tweak optimal_nop test to be host independent.Daniel Dunbar2010-03-202-6/+232
| | | | | | - This also avoids us running valgrind on /usr/bin/as, which has leaks. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99099 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed the encoding problems of the crc32 instructions. All had the Operand sizeKevin Enderby2010-03-194-25/+150
| | | | | | | | | | override prefix and only the r/m16 forms should have had that. Also for variant one, the AT&T syntax, added suffixes to all forms. Also added the missing 64-bit form for 'CRC32 r64, r/m8'. Plus added test cases for all forms and tweaked one test case to add the needed suffixes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98980 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/Mach-O/x86_64: Add relocation support.Daniel Dunbar2010-03-193-0/+901
| | | | | | | | - This is "extraordinarily" Darwin 'as' compatible. See the litany of FIXMEs littered about for more information. - There are a few cases which seem to clearly be 'as' bugs which I have left unsupported, and there is one cases where we diverge but should fix if it blocks diffing .o files (Darwin 'as' ends up widening a jump unnecessarily). - 403.gcc build, runs, and diffs equivalently to the 'as' built version now (using llvm-mc). However, it builds so slowly that I wouldn't recommend trying it quite yet. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98974 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/X86: Rename alternate spellings of {ADD64,CMP64} and mark as "code gen ↵Daniel Dunbar2010-03-191-0/+4
| | | | | | only" so they don't get selected by the asm matcher. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98972 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/Mach-O: Factor out isScatteredFixupFullyResolvedSimple predicate, and fix ↵Daniel Dunbar2010-03-191-45/+73
| | | | | | some corner cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98924 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Fix encoding for TEST64rr.Daniel Dunbar2010-03-191-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98919 91177308-0d34-0410-b5e6-96231b3b80d8
* X86MCCodeEmitter: Fix two minor issues with reloc_riprel_4byte_movq_load, weDaniel Dunbar2010-03-181-1/+6
| | | | | | | were missing it on some movq instructions and were not including the appropriate PCrel bias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98880 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/X86/AsmMatcher: Use the new instruction cleanup routine to implement aDaniel Dunbar2010-03-181-0/+26
| | | | | | | | temporary workaround for matching inc/dec on x86_64 to the correct instruction. - This hack will eventually be replaced with a robust mechanism for handling matching instructions based on the available target features. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98858 91177308-0d34-0410-b5e6-96231b3b80d8
* fix an x86-64 encoding bug Daniel found.Chris Lattner2010-03-181-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98855 91177308-0d34-0410-b5e6-96231b3b80d8
* add a special relocation type for movq loads for objectChris Lattner2010-03-181-1/+9
| | | | | | | | files that produce special relocation types where the linker changes movq's into lea's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98839 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/Mach-O/x86_64: Temporary labels in cstring sections require symbols (and ↵Daniel Dunbar2010-03-152-0/+2039
| | | | | | external relocations, but we don't have x86_64 relocations yet). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98583 91177308-0d34-0410-b5e6-96231b3b80d8
* xfail properlyChris Lattner2010-03-141-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98479 91177308-0d34-0410-b5e6-96231b3b80d8
* xfail these tests temporarily to get teh buildbots back to happy land.Chris Lattner2010-03-144-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98476 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Fix ADD64i32 encoding.Daniel Dunbar2010-03-131-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98457 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/X86_64: Symbol support.Daniel Dunbar2010-03-131-144/+293
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98456 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/Mach-O: Initial x86_64 support.Daniel Dunbar2010-03-132-7/+564
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98454 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/X86_64: Fix matching of leaq.Daniel Dunbar2010-03-131-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98444 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/X86_64: Fix matching of callq.Daniel Dunbar2010-03-131-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98443 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/Mach-O: PCrel relocations weren't using the right base address, they areDaniel Dunbar2010-03-131-0/+14
| | | | | | | relative to the fragment address, not its offset. This was masked by the text section normally being at address 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98420 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/X86: Add temporary hack to match shrl $1,%eax correctly, to support testingDaniel Dunbar2010-03-131-0/+3
| | | | | | other functionality on 403.gcc compiled at -O0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98405 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/X86: Add an XFAIL test where we aren't matching the correct instructionDaniel Dunbar2010-03-131-0/+8
| | | | | | | because we don't understand how the specific instruction is doing sign extension. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98404 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/Mach-O: Implement initial support for relaxation.Daniel Dunbar2010-03-122-0/+68
| | | | | | | | | | | | - The implementation is currently very brain dead and inefficient, but I have a clear plan on how to fix it. - The good news is, it works and correctly assembles 403.gcc (when built with Clang, at '-Os', '-Os -g', and '-O3'). Even better, at '-Os' and '-Os -g', the resulting binary is exactly equivalent to that when built with the system assembler. So it probably works! :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98396 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/Mach-O: Implement "absolutizing" semantics of .set, by evaluating the ↵Daniel Dunbar2010-03-111-0/+71
| | | | | | assembly time value of variables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98241 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-01-31 05:03:15 +0000