aboutsummaryrefslogtreecommitdiffstats
path: root/test/MC
Commit message (Collapse)AuthorAgeFilesLines
* Add a test for .seh_pushframe parsing. Fix the bug exposed by it (and anotherCharles Davis2011-05-251-0/+2
| | | | | | | one I found by inspection). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132037 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test for the .seh_handler directive. Fix problems with the parsingCharles Davis2011-05-251-4/+6
| | | | | | | | method exposed by the test. While we're at it, simplify the .seh_proc parsing method. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132028 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR9762Bruno Cardoso Lopes2011-05-251-0/+3
| | | | | | Enable the parsing of the operand "cpsr_all" for the ARM msr instruction git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132026 91177308-0d34-0410-b5e6-96231b3b80d8
* Test basic SEH directive-parsing functionality. Fix a latent bug exposed byCharles Davis2011-05-241-0/+18
| | | | | | | this test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132004 91177308-0d34-0410-b5e6-96231b3b80d8
* add test from PR9164Chris Lattner2011-05-221-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131876 91177308-0d34-0410-b5e6-96231b3b80d8
* testcase for PR9378Chris Lattner2011-05-221-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131875 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Bug 9386 - ARM disassembler failed to disassemble conditional bxJohnny Chen2011-05-221-0/+3
| | | | | | | | Modified the patch to .td file supplied by Jyun-Yan You. Add a test case and modified ARMDisassemblerCore.cpp a little bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131859 91177308-0d34-0410-b5e6-96231b3b80d8
* adds some attributes to attribute section when cpu is "xscale"Rafael Espindola2011-05-201-0/+31
| | | | | | | | (this is what used in Android NDK, when architecture is ARMv5) patch by Koan-Sin Tan git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131751 91177308-0d34-0410-b5e6-96231b3b80d8
* fixes target address tBL and tBLX and sets relocation typeRafael Espindola2011-05-201-0/+37
| | | | | | | | of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6) Patch by koan-sin tan. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131748 91177308-0d34-0410-b5e6-96231b3b80d8
* This fixes one divergence between LLVM and binutils for ARM in theJason W Kim2011-05-191-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | text section. Assume the following bit of annotated assembly: .section .data.rel.ro,"aw",%progbits .align 2 .LAlpha: .long startval(GOTOFF) .text .align 2 .type main,%function .align 4 main: ;;; assume "main" starts at offset 0x20 0x0 push {r11, lr} 0x4 movw r0, :lower16:(.LAlpha-(.LBeta+8)) ;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8) ;;; ==> (??? - ((16-4) + 8) = -20 0x8 movt r0, :upper16:(.LAlpha-(.LBeta+8)) ;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8) ;;; ==> (??? - ((16-8) + 8) = -16 0xc ... blah .LBeta: 0x10 add r0, pc, r0 0x14 ... blah .LGamma: 0x18 add r1, pc, r1 Above snippet results in the following relocs in the .o file for the first pair of movw/movt instructions 00000024 R_ARM_MOVW_PREL_NC .LAlpha 00000028 R_ARM_MOVT_PREL .LAlpha And the encoded instructions in the .o file for main: must be 00000020 <main>: 20: e92d4800 push {fp, lr} 24: e30f0fec movw r0, #65516 ; 0xffec i.e. -20 28: e34f0ff0 movt r0, #65520 ; 0xfff0 i.e. -16 However, llc (prior to this commit) generates the following sequence 00000020 <main>: 20: e92d4800 push {fp, lr} 24: e30f0fec movw r0, #65516 ; 0xffec - i.e. -20 28: e34f0fff movt r0, #65535 ; 0xffff - i.e. -1 What has to happen in the ArmAsmBackend is that if the relocation is PC relative, the 16 bits encoded as part of movw and movt must be both addends, not addresses. It makes sense to encode addresses by right shifting the value by 16, but the result is incorrect for PIC. i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case. This change agrees with what GNU as does, and makes the PIC code run. MC/ARM/elf-movt.s covers this case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131674 91177308-0d34-0410-b5e6-96231b3b80d8
* ADD64ri32 sign extends its argument, so we need to use a R_X86_64_32S.Rafael Espindola2011-05-191-0/+7
| | | | | | | | Fixes PR9934. We really need to start tblgening the relocation info :-( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131669 91177308-0d34-0410-b5e6-96231b3b80d8
* Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' ↵Johnny Chen2011-05-181-0/+3
| | | | | | immediate operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131565 91177308-0d34-0410-b5e6-96231b3b80d8
* sets bit 0 of the function address of thumb function in .symtabRafael Espindola2011-05-161-0/+20
| | | | | | | | | | ("T is 1 if the target symbol S has type STT_FUNC and the symbol addresses a Thumb instruction ;it is 0 otherwise." from "ELF for the ARM Architecture" 4.7.1.2) Patch by Koan-Sin Tan! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131406 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan.Owen Anderson2011-05-111-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131189 91177308-0d34-0410-b5e6-96231b3b80d8
* On MachO, unlike ELF, there should be no relocation to produce the CIE pointer.Rafael Espindola2011-05-101-0/+38
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131149 91177308-0d34-0410-b5e6-96231b3b80d8
* In a debug_frame the cfi offset is to the start of the debug_frame section!Rafael Espindola2011-05-101-6/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131129 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for producing .deubg_frame sections.Rafael Espindola2011-05-101-0/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131121 91177308-0d34-0410-b5e6-96231b3b80d8
* Explicitly request -join-physregs for some tests that depend on it.Jakob Stoklund Olesen2011-05-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130855 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some random comments that snuck in from somewhere.Eric Christopher2011-05-041-4/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130812 91177308-0d34-0410-b5e6-96231b3b80d8
* xmm0 is an implicit parameter in this and so shouldn't be in theEric Christopher2011-05-031-0/+9
| | | | | | | | | string template. Fixes rdar://8493866 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130747 91177308-0d34-0410-b5e6-96231b3b80d8
* MCAsmLayout: Add support for computing the symbol offset of variables. NotDaniel Dunbar2011-04-291-0/+8
| | | | | | currently used, because variables don't get reported as being "defined". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130524 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Change variable symbols to be recognized as defined, by assigning their ↵Daniel Dunbar2011-04-291-0/+446
| | | | | | sections based on FindAssociatedSection(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130523 91177308-0d34-0410-b5e6-96231b3b80d8
* Add tests for A8.6.110 NOP.Johnny Chen2011-04-272-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130345 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some hard coded CR-LFs. Some of these were the entire files, one ofChandler Carruth2011-04-256-498/+498
| | | | | | | | these was just one line of a file. Explicitly set the eol-style property on the files to try and ensure this fix stays. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130125 91177308-0d34-0410-b5e6-96231b3b80d8
* Disassembly of A8.6.59 LDR (literal) Encoding T1 (16-bit thumb instruction) ↵Johnny Chen2011-04-222-3/+6
| | | | | | | | | | | should print out ldr, not ldr.n. rdar://problem/9267772 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130008 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix relative relocations. This is sufficient for running the rust testsuite withRafael Espindola2011-04-211-3/+21
| | | | | | MC :-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129923 91177308-0d34-0410-b5e6-96231b3b80d8
* Behave like gnu as when a relocation crosses sections.Rafael Espindola2011-04-201-0/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129850 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 BFC was insufficiently encoded.Johnny Chen2011-04-151-0/+3
| | | | | | | rdar://problem/9292717 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129619 91177308-0d34-0410-b5e6-96231b3b80d8
* A8.6.315 VLD3 (single 3-element structure to all lanes)Johnny Chen2011-04-151-0/+11
| | | | | | | | | The a bit must be encoded as 0. rdar://problem/9292625 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129618 91177308-0d34-0410-b5e6-96231b3b80d8
* Add encoding tests for flds/fildsJoerg Sonnenberger2011-04-152-0/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129589 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-1/+1
| | | | | | | | Luis Felipe Strano Moraes! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
* The ARM disassembler did not handle the alignment correctly for VLD*DUP* ↵Johnny Chen2011-04-152-0/+16
| | | | | | | | | instructions (single element or n-element structure to all lanes). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129550 91177308-0d34-0410-b5e6-96231b3b80d8
* Add sanity checkings for Thumb2 Load/Store Register Exclusive family of ↵Johnny Chen2011-04-144-0/+33
| | | | | | operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129531 91177308-0d34-0410-b5e6-96231b3b80d8
* As Dan pointed out, movzbl, movsbl, and friends are nicer than their aliasBill Wendling2011-04-141-26/+26
| | | | | | | (movzx/movsx) because they give more information. Revert that part of the patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129498 91177308-0d34-0410-b5e6-96231b3b80d8
* Have the X86 back-end emit the alias instead of what's being aliased. In mostBill Wendling2011-04-142-70/+70
| | | | | | | cases, it's much nicer and more informative reading the alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129497 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb disassembler did not handle tBRIND (indirect branch) properly.Johnny Chen2011-04-131-0/+3
| | | | | | | rdar://problem/9280370 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129480 91177308-0d34-0410-b5e6-96231b3b80d8
* Check for unallocated instruction encodings when disassembling Thumb Branch ↵Johnny Chen2011-04-132-2/+13
| | | | | | | | | instructions (tBcc and t2Bcc). rdar://problem/9280470 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129471 91177308-0d34-0410-b5e6-96231b3b80d8
* The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.Johnny Chen2011-04-131-0/+10
| | | | | | | rdar://problem/9279440 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129469 91177308-0d34-0410-b5e6-96231b3b80d8
* Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings ↵Johnny Chen2011-04-132-0/+20
| | | | | | | | | as such. rdar://problem/9276651 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129462 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was ↵Johnny Chen2011-04-131-0/+3
| | | | | | | | | not properly handled. rdar://problem/9276427 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129456 91177308-0d34-0410-b5e6-96231b3b80d8
* Add sanity check for Ld/St Dual forms of Thumb2 instructions.Johnny Chen2011-04-122-0/+23
| | | | | | | rdar://problem/9273947 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129411 91177308-0d34-0410-b5e6-96231b3b80d8
* The Thumb2 RFE instructions need to have their second halfword fully specified.Johnny Chen2011-04-121-0/+3
| | | | | | | | | | | In addition, the base register is not rGPR, but GPR with th exception that: if n == 15 then UNPREDICTABLE rdar://problem/9273836 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129391 91177308-0d34-0410-b5e6-96231b3b80d8
* Add bad register checks for Thumb2 Ld/St instructions.Johnny Chen2011-04-121-0/+10
| | | | | | | rdar://problem/9269047 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129387 91177308-0d34-0410-b5e6-96231b3b80d8
* The Thumb2 Ld, St, and Preload instructions with the i12 forms should have ↵Johnny Chen2011-04-121-1/+13
| | | | | | | | | | | its Inst{23} be specified as '1' (add = TRUE). Also add a utility function for Thumb2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129377 91177308-0d34-0410-b5e6-96231b3b80d8
* Print out a debug message when the reglist fails the sanity check for Thumb ↵Johnny Chen2011-04-121-0/+10
| | | | | | Ld/St Multiple. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129365 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the case of a .cfi_rel_offset before any .cfi_def_cfa_offset.Rafael Espindola2011-04-121-0/+41
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129362 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement .cfi_same_value.Rafael Espindola2011-04-121-0/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129361 91177308-0d34-0410-b5e6-96231b3b80d8
* Add one test case (svc).Johnny Chen2011-04-121-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129327 91177308-0d34-0410-b5e6-96231b3b80d8
* Match case for invalid constant error messages and add a newEric Christopher2011-04-121-1/+4
| | | | | | | test for invalid hexadecimals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129326 91177308-0d34-0410-b5e6-96231b3b80d8
* A8.6.16 BJohnny Chen2011-04-121-0/+10
| | | | | | | | | | Encoding T1 (tBcc) if cond == '1110' then UNDEFINED; rdar://problem/9268681 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129325 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-02-04 00:52:19 +0000