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* Fixed an assert by the ARM disassembler for LDRD_PRE/POST.Johnny Chen2011-03-191-0/+3
| | | | | | | | | The relevant instruction table entries were changed sometime ago to no longer take <Rt2> as an operand. Modify ARMDisassemblerCore.cpp to accomodate the change and add a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127935 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support to the ARM asm parser for the register-shifted-register forms of ↵Owen Anderson2011-03-181-0/+2
| | | | | | basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127917 91177308-0d34-0410-b5e6-96231b3b80d8
* Support explicit argument forms for the X86 string instructions.Joerg Sonnenberger2011-03-182-0/+245
| | | | | | | For now, only the default segments are supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127875 91177308-0d34-0410-b5e6-96231b3b80d8
* The disassembler for Thumb was wrongly adding 4 to the computed imm32 offset.Johnny Chen2011-03-181-3/+3
| | | | | | | Remove the offending logic and update the test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127843 91177308-0d34-0410-b5e6-96231b3b80d8
* It used to be that t_addrmode_s4 was used for both:Johnny Chen2011-03-171-0/+9
| | | | | | | | | | | | o A8.6.195 STR (register) -- Encoding T1 o A8.6.193 STR (immediate, Thumb) -- Encoding T1 It has been changed so that now they use different addressing modes and thus different MC representation (Operand Infos). Modify the disassembler to reflect the change, and add relevant tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127833 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/Mach-O: Fix regression introduced in r126127, this assignment shouldn't haveDaniel Dunbar2011-03-171-0/+7
| | | | | | been removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127812 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix handling of @IDNTPOFF relocations, they need to get STT_TLS.Joerg Sonnenberger2011-03-171-0/+10
| | | | | | | While here, add VK_ARM_TPOFF and VK_ARM_GOTTPOFF, too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127780 91177308-0d34-0410-b5e6-96231b3b80d8
* There were two issues fixed:Johnny Chen2011-03-151-1/+7
| | | | | | | | | | | | | | | | | 1. The ARM Darwin *r9 call instructions were pseudo-ized recently. Modify the ARMDisassemblerCore.cpp file to accomodate the change. 2. The disassembler was unnecessarily adding 8 to the sign-extended imm24: imm32 = SignExtend(imm24:'00', 32); // A8.6.23 BL, BLX (immediate) // Encoding A1 It has no business doing such. Removed the offending logic. Add test cases to arm-tests.txt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127707 91177308-0d34-0410-b5e6-96231b3b80d8
* Basic sanity checks to ensure that 2- and 3-byteSean Callanan2011-03-151-0/+6
| | | | | | | | | VEX prefixes are working for triadic AVX instructions. This concludes the patch set to enable AVX support for the X86 disassebler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127647 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed an ARM disassembler bug where it does not handle STRi12 correctly ↵Johnny Chen2011-03-151-0/+12
| | | | | | | | | | | because an extra register operand was erroneously added. Remove an incorrect assert which triggers the bug. rdar://problem/9131529 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127642 91177308-0d34-0410-b5e6-96231b3b80d8
* Roll r127459 back in:Cameron Zwarich2011-03-111-1/+1
| | | | | | | | | | | Optimize trivial branches in CodeGenPrepare, which often get created from the lowering of objectsize intrinsics. Unfortunately, a number of tests were relying on llc not optimizing trivial branches, so I had to add an option to allow them to continue to test what they originally tested. This fixes <rdar://problem/8785296> and <rdar://problem/9112893>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127498 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often getDaniel Dunbar2011-03-111-1/+1
| | | | | | created from the", it broke some GCC test suite tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127477 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize trivial branches in CodeGenPrepare, which often get created from theCameron Zwarich2011-03-111-1/+1
| | | | | | | | | | lowering of objectsize intrinsics. Unfortunately, a number of tests were relying on llc not optimizing trivial branches, so I had to add an option to allow them to continue to test what they originally tested. This fixes <rdar://problem/8785296> and <rdar://problem/9112893>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127459 91177308-0d34-0410-b5e6-96231b3b80d8
* LLVM combines the offset mode of A8.6.199 A1 & A2 into STRBT.Johnny Chen2011-03-091-0/+3
| | | | | | | | | | The insufficient encoding information of the combined instruction confuses the decoder wrt UQADD16. Add extra logic to recover from that. Fixed an assert reported by Sean Callanan git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127354 91177308-0d34-0410-b5e6-96231b3b80d8
* * Correct encoding for VSRI.Bill Wendling2011-03-091-0/+32
| | | | | | | * Add tests for VSRI and VSLI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127297 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct the encoding for VRSRA and VSRA instructions.Bill Wendling2011-03-091-0/+32
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127294 91177308-0d34-0410-b5e6-96231b3b80d8
* * Fix VRSHR and VSHR to have the correct encoding for the immediate.Bill Wendling2011-03-081-109/+108
| | | | | | | * Update the NEON shift instruction test to expect what 'as' produces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127293 91177308-0d34-0410-b5e6-96231b3b80d8
* A few more tests for instruction encodings.Bill Wendling2011-03-081-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127209 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename the narrow shift right immediate operands to "shr_imm*" operands. AlsoBill Wendling2011-03-071-0/+5
| | | | | | | | | expand the testing of the narrowing shift right instructions. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127193 91177308-0d34-0410-b5e6-96231b3b80d8
* Be nice to Xcore and the XMOS assembler and avoid quoting section namesJoerg Sonnenberger2011-03-041-1/+1
| | | | | | | that contain only letters, digits and the characters "_" and ".". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127028 91177308-0d34-0410-b5e6-96231b3b80d8
* Followup to r126970: add 64-bit encoding tests for str with reg operand.Eli Friedman2011-03-041-0/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126987 91177308-0d34-0410-b5e6-96231b3b80d8
* PR9377: Handle x86 str with register operand in a way consistent with gas.Eli Friedman2011-03-041-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126970 91177308-0d34-0410-b5e6-96231b3b80d8
* Bug#9033: For the ELF assembler output, always quote the section name.Joerg Sonnenberger2011-03-031-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126963 91177308-0d34-0410-b5e6-96231b3b80d8
* PR9352: Always emit a relocation for weak symbols. Not emitting relocationsEli Friedman2011-03-031-0/+15
| | | | | | | | | | for calls to weak symbols with a definition has the appearance of working with LLVM-generated code because weak symbol definitions are put in their own sections. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126933 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen should not ignore BX instructions for the ARM disassembler. pr9368.Bob Wilson2011-03-031-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126931 91177308-0d34-0410-b5e6-96231b3b80d8
* pr9367: Add missing predicated BLX instructions.Bob Wilson2011-03-031-0/+3
| | | | | | Patch by Jyun-Yan You, with some minor adjustments and a testcase from me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126915 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixes an assertion failure while disassembling ARM rsbs reg/reg form.Kevin Enderby2011-03-021-0/+3
| | | | | | | Patch by Ted Kremenek! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126895 91177308-0d34-0410-b5e6-96231b3b80d8
* Narrow right shifts need to encode their immediates differently from a normalBill Wendling2011-03-011-0/+2
| | | | | | | | | | | shift. 16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0> 32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0> 64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the arm's disassembler for blx that was building an MCInst without theKevin Enderby2011-02-281-0/+3
| | | | | | | needed two predicate operands before the imm operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126662 91177308-0d34-0410-b5e6-96231b3b80d8
* split this test into arch specific pieces, so the ARMChris Lattner2011-02-252-1/+15
| | | | | | | | test isn't run when the arm backend isn't built. This fixes PR9327 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126500 91177308-0d34-0410-b5e6-96231b3b80d8
* Restore r125595 (reverted in r126336) with modifications:Joerg Sonnenberger2011-02-243-0/+29
| | | | | | | | Introduce a variable in the AsmParserExtension whether [] is valid in an expression. If it is true, parse them like (). Enable this for ELF only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126443 91177308-0d34-0410-b5e6-96231b3b80d8
* Move arch specific tests in arch specific directories.Devang Patel2011-02-243-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126401 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove file. Previous commit deleted content, but left the file around.Jim Grosbach2011-02-231-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126337 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r125595, which is an X86-only undocumented assembly syntax extensionJim Grosbach2011-02-232-10/+0
| | | | | | | | | | | | enabled for all targets. Non-X86 targets should not have this behavior enabled by default. Joerg, if you would like to resubmit with the behavior conditionalized to be X86-ELF only, that's fine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126336 91177308-0d34-0410-b5e6-96231b3b80d8
* Put in the symbol table symbols only used in a .globl statement.Rafael Espindola2011-02-231-0/+26
| | | | | | Fixes PR9292. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126330 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a bug in the enhanced disassembler that causedSean Callanan2011-02-231-0/+2
| | | | | | | | | it to ignore valid uses of FS and GS as additional base registers in address computations. Added a test case for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126302 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the same (%dx) hack for in[bwl] as for out[bwl].Joerg Sonnenberger2011-02-221-3/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126244 91177308-0d34-0410-b5e6-96231b3b80d8
* Added a testcase for the enhanced disassembly bugSean Callanan2011-02-221-0/+4
| | | | | | | | fixed in r126147, where a field in the X86 decode structure was being read as bits, not bytes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126182 91177308-0d34-0410-b5e6-96231b3b80d8
* Recognize loopz and loopnz as aliases for loope and loopne.Joerg Sonnenberger2011-02-222-0/+16
| | | | | | | From Dimitry Andric. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126168 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement xgetbv and xsetbv.Rafael Espindola2011-02-221-0/+4
| | | | | | Patch by Jai Menon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126165 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle FK_PCRel_1 and add a test case for this and FK_PCRel_4.Joerg Sonnenberger2011-02-211-0/+33
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126157 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some limited support for labels in org directives. Hopefully enough to fixRafael Espindola2011-02-201-0/+13
| | | | | | PR9245. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126091 91177308-0d34-0410-b5e6-96231b3b80d8
* implement PR9264: disambiguating 'bt mem, imm' as a btl.Chris Lattner2011-02-191-0/+4
| | | | | | | | This is reasonable to do since all bt-mem forms do the same thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126047 91177308-0d34-0410-b5e6-96231b3b80d8
* Add assembly parsing support for "msr" and also fix its encoding. Also addBruno Cardoso Lopes2011-02-184-0/+67
| | | | | | | | testcases for the disassembler to make sure it still works for "msr". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125948 91177308-0d34-0410-b5e6-96231b3b80d8
* Recognize monitor/mwait with explicit register argumentsJoerg Sonnenberger2011-02-182-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125805 91177308-0d34-0410-b5e6-96231b3b80d8
* Recognize leavel and leaveq aliases for leave.Joerg Sonnenberger2011-02-172-0/+14
| | | | | | | Validate encoding of leave in 64bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125795 91177308-0d34-0410-b5e6-96231b3b80d8
* Gas is very inconsistent about when a relaxation/relocation is needed. DoRafael Espindola2011-02-161-17/+3
| | | | | | the right thing and stop trying to copy it. Fixes PR8944. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125648 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for pushsection and popsection. Patch by Joerg Sonnenberger.Rafael Espindola2011-02-161-0/+107
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125629 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for parsing [expr].Roman Divacky2011-02-152-0/+10
| | | | | | | | This is submitted by Joerg Sonnenberger and fixes his PR8685. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125595 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix encoding and add parsing support for the arm/thumb CPS instruction:Bruno Cardoso Lopes2011-02-145-0/+40
| | | | | | | | | | | | | | - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125489 91177308-0d34-0410-b5e6-96231b3b80d8
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