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* COFF: Ensure that objects produced by LLVM link with /safesehReid Kleckner2013-09-171-0/+13
| | | | | | | | | | | | | | | | | | | | Summary: We indicate that the object files are safe by emitting a @feat.00 absolute address symbol. The address is presumably interpreted as a bitfield of features that the compiler would like to enable. Bit 0 is documented in the PE COFF spec to opt in to "registered SEH", which is what /safeseh enables. LLVM's object files are safe by default because LLVM doesn't know how to produce SEH handlers. Reviewers: Bigcheese CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1691 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190898 91177308-0d34-0410-b5e6-96231b3b80d8
* COFF: Emit all MCSymbols rather than filtering out some of themReid Kleckner2013-09-171-1/+10
| | | | | | | | | | In particular, this means we emit non-external symbols defined to variables, such as aliases or absolute addresses. This is needed to implement /safeseh, and it appears there was some confusion about what symbols to emit previously. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190888 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Fix the deprecation of MCR encodings that map to CP15{ISB,DSB,DMB}.Joey Gouly2013-09-171-3/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190862 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement 3 AArch64 neon instructions : umov smov ins.Kevin Qin2013-09-171-0/+71
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190839 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch implements Mips load/store instructions from/to coprocessor 2. ↵Vladimir Medic2013-09-161-0/+8
| | | | | | Test cases are added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190780 91177308-0d34-0410-b5e6-96231b3b80d8
* ELF: Add support for the exclude section bit for gas compat.Benjamin Kramer2013-09-151-4/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190769 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Add support for '?' flags in .section directivesDavid Majnemer2013-09-151-1/+1
| | | | | | | | | | | | | | | | | | | Summary: The '?' flag uses the last section group if the last had a section group. We treat combining an explicit section group and the '?' as a hard error. This fixes PR17198. Reviewers: rafael, bkramer Reviewed By: bkramer CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1686 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190768 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix alignment of unwind data.Kai Nacke2013-09-153-0/+226
| | | | | | | | | | | | For alignment purposes, the instruction array will always have an even number of entries, with the final entry potentially unused (in which case the array will be one longer than indicated by the count of unwind codes field). Reviewed by Anton Korobeynikov, Charles Davis and Nico Rieck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190767 91177308-0d34-0410-b5e6-96231b3b80d8
* Generate IMAGE_REL_AMD64_ADDR32NB relocations for SEHKai Nacke2013-09-151-1/+22
| | | | | | | | | | | | | | | data structures. The Win64 EH data structures must be of type IMAGE_REL_AMD64_ADDR32NB instead of IMAGE_REL_AMD64_ADDR32. This is easiely achieved by adding the VK_COFF_IMGREL32 modifier to the symbol reference. Change also references to start and end of the SEH range of a function as offsets to start of the function. Reviewed by Jim Grosbach, Charles Davis and Nico Rieck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190766 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the remaining Intel SHA instructionsBen Langmuir2013-09-142-1/+89
| | | | | | | | Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit xmm0 dependency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190754 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed bug when generating Load Upper Immediate microMIPS instruction.Zoran Jovanovic2013-09-143-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190746 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for microMIPS DIV instructions.Zoran Jovanovic2013-09-143-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190745 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for misc microMIPS instructions.Zoran Jovanovic2013-09-142-0/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190744 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix tests for hasFPARMv8 name change (r190692)Amaury de la Vieuville2013-09-135-5/+5
| | | | | | Patch by Bradley Smith git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190694 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Change hasV8Fp to hasFPARMv8, and other command line optionsJoey Gouly2013-09-131-1/+1
| | | | | | | | to be more consistent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190692 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: use RegisterOperand for NEON registers.Tim Northover2013-09-132-6/+11
| | | | | | | | | | | | | | | | Previously we modelled VPR128 and VPR64 as essentially identical register-classes containing V0-V31 (which had Q0-Q31 as "sub_alias" sub-registers). This model is starting to cause significant problems for code generation, particularly writing EXTRACT/INSERT_SUBREG patterns for converting between the two. The change here switches to classifying VPR64 & VPR128 as RegisterOperands, which are essentially aliases for RegisterClasses with different parsing and printing behaviour. This fits almost exactly with their real status (VPR128 == FPR128 printed strangely, VPR64 == FPR64 printed strangely). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190665 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement asm support for a few PowerPC bookIII that are needed for assemblingRoman Divacky2013-09-121-0/+107
| | | | | | | FreeBSD kernel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190618 91177308-0d34-0410-b5e6-96231b3b80d8
* Partial support for Intel SHA Extensions (sha1rnds4)Ben Langmuir2013-09-122-0/+14
| | | | | | | | | | Add basic assembly/disassembly support for the first Intel SHA instruction 'sha1rnds4'. Also includes feature flag, and test cases. Support for the remaining instructions will follow in a separate patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190611 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark PPC MFTB and DST (and friends) as deprecatedHal Finkel2013-09-121-0/+12
| | | | | | | | Use the new instruction deprecation feature to mark mftb (now replaced with mfspr) and dst (along with the other Altivec cache control instructions) as deprecated when targeting cores supporting at least ISA v2.03. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190605 91177308-0d34-0410-b5e6-96231b3b80d8
* Somehow this important part of the patch, where I actually check the Mask,Joey Gouly2013-09-121-3/+6
| | | | | | | | | got lost during my iterations of review. Thanks to Hal for spotting it! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190604 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | The 'Deprecated' class allows you to specify a SubtargetFeature that the instruction is deprecated on. The 'ComplexDeprecationPredicate' class allows you to define a custom predicate that is called to check for deprecation. For example: ComplexDeprecationPredicate<"MCR"> would mean you would have to define the following function: bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) Which returns 'false' for not deprecated, and 'true' for deprecated and store the warning message in 'Info'. The MCTargetAsmParser constructor was chaned to take an extra argument of the MCInstrInfo class, so out-of-tree targets will need to be changed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190598 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: implemented extractelement with variable index.Elena Demikhovsky2013-09-121-1/+9
| | | | | | | Added parsing of mask register and "zeroing" semantic, like {%k1} {z}. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190595 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add TM and TMYRichard Sandiford2013-09-103-0/+123
| | | | | | | | | | | | | | | | | | | | | | | | The main complication here is that TM and TMY (the memory forms) set CC differently from the register forms. When the tested bits contain some 0s and some 1s, the register forms set CC to 1 or 2 based on the value the uppermost bit. The memory forms instead set CC to 1 regardless of the uppermost bit. Until now, I've tried to make it so that a branch never tests for an impossible CC value. E.g. NR only sets CC to 0 or 1, so branches on the result will only test for 0 or 1. Originally I'd tried to do the same thing for TM and TMY by using custom matching code in ISelDAGToDAG. That ended up being very ugly though, and would have meant duplicating some of the chain checks that the common isel code does. I've therefore gone for the simpler alternative of adding an extra operand to the TM DAG opcode to say whether a memory form would be OK. This means that the inverse of a "TM;JE" is "TM;JNE" rather than the more precise "TM;JNLE", just like the inverse of "TMLL;JE" is "TMLL;JNE". I suppose that's arguably less confusing though... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190400 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test cases for Mips mthc1/mfhc1 instructions. Add check for odd value of ↵Vladimir Medic2013-09-101-0/+4
| | | | | | register when PFU is 32 bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190397 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement aarch64 neon instruction set AdvSIMD (3V Diff), covering the ↵Jiangning Liu2013-09-093-0/+1510
| | | | | | | | | | following 26 instructions, SADDL, UADDL, SADDW, UADDW, SSUBL, USUBL, SSUBW, USUBW, ADDHN, RADDHN, SABAL, UABAL, SUBHN, RSUBHN, SABDL, UABDL, SMLAL, UMLAL, SMLSL, UMLSL, SQDMLAL, SQDMLSL, SMULL, UMULL, SQDMULL, PMULL git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190288 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Add definition of instruction "drotr32" (double rotate right plus 32).Akira Hatanaka2013-09-071-1/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190232 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Set instruction itineraries of loads, stores and conditional moves.Akira Hatanaka2013-09-061-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190219 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds support for microMIPS Multiply and Add/Sub instructions. ↵Vladimir Medic2013-09-063-0/+50
| | | | | | Test cases are included in patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190154 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds support for microMIPS Move to/from HI/LO instructions. Test ↵Vladimir Medic2013-09-062-0/+24
| | | | | | cases are included in patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190152 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds support for microMIPS Move Conditional instructions. Test ↵Vladimir Medic2013-09-063-0/+50
| | | | | | cases are included in patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190148 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds support for microMIPS disassembler and disassembler make ↵Vladimir Medic2013-09-062-0/+298
| | | | | | check tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190144 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a crash in the integrated assembler for Mach-O when a symbol differenceKevin Enderby2013-09-051-0/+38
| | | | | | | | | | | | | | expression uses an assembler temporary symbol from an assignment.  In this case the symbol does not have a fragment so the use of getFragment() would be NULL and caused a crash. In the case of an assembler temporary symbol we want to use the AliasedSymbol (if any) which will create a local relocation entry, but if it is not an assembler temporary symbol then let it use that symbol with an external relocation entry. rdar://9356266 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190096 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve handling of .file, .include and .incbin directives toYunzhong Gao2013-09-053-3/+3
| | | | | | | | | | | allow escaped octal character sequences. The patch was discussed in Phabricator. See: http://llvm-reviews.chandlerc.com/D1289 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190089 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add some missing tests for DSB/DMB.Joey Gouly2013-09-053-3/+57
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190060 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Implement the new DMB/DSB operands.Joey Gouly2013-09-051-1/+36
| | | | | | | | | This removes the custom ISD Node: MEMBARRIER and replaces it with an intrinsic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190055 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AArch32 DCPS{1,2,3} and HLT instructions.Richard Barton2013-09-056-0/+119
| | | | | | | | | | | | | | | | | | | These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190053 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add NC, OC and XCRichard Sandiford2013-09-053-0/+318
| | | | | | | | For now these are just used to handle scalar ANDs, ORs and XORs in which all operands are memory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190041 91177308-0d34-0410-b5e6-96231b3b80d8
* Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift ↵Hao Liu2013-09-043-3/+1552
| | | | | | | | | | | instructions: sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll and 4 convert instructions: scvtf,ucvtf,fcvtzs,fcvtzu git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189925 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a bug where diassembling an instruction that had a prefix would cause ↵Richard Mitton2013-08-301-0/+59
| | | | | | LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189698 91177308-0d34-0410-b5e6-96231b3b80d8
* The darwin integrated assembler for X86 in 64-bit mode is not rejectingKevin Enderby2013-08-291-0/+5
| | | | | | | | | | | | | 32-bit absolute addressing in instructions likei this: mov $_f, %rsi which is not supported in 64-bit mode. rdar://8827134 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189543 91177308-0d34-0410-b5e6-96231b3b80d8
* The integrated darwin assembler can hang in an infinite loop (or get an assert Kevin Enderby2013-08-281-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | with a debug build) with this buggy .indirect_symbol directive usage: % cat test.s x: .indirect_symbol _y The assertion is because it is trying to get the symbol index for the symbol _y when it is writing out the indirect symbol table. This line of code in MachObjectWriter::WriteObject() : Write32(Asm.getSymbolData(*it->Symbol).getIndex()); And while there is a symbol _y it does not have any getSymbolData set which is only done in MachObjectWriter::BindIndirectSymbols() for pointer sections or stub sections. I added a check and an error in there to catch this in case something slips through. But to get a better error the parser should detect when a .indirect_symbol directive is used and it is not in a pointer section or stub section. To make that work I moved the handling of the indirect symbol out of the target independent AsmParser code into the DarwinAsmParser code that can check for the proper Mach-O section types. rdar://14825505 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189497 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8]Joey Gouly2013-08-282-0/+30
| | | | | | | | | | | | Fix a few things in one swoop. # Add some negative tests. # Fix some formatting issues. # Add some missing IsThumb / ARMv8 # Fix some outs / ins mistakes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189490 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add support for TMHH, TMHL, TMLH and TMLLRichard Sandiford2013-08-283-0/+120
| | | | | | | | | | For now just handles simple comparisons of an ANDed value with zero. The CC value provides enough information to do any comparison for a 2-bit mask, and some nonzero comparisons with more populated masks, but that's all future work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189469 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Use ptr_rc to simplify definitions of base+index load/store instructions.Akira Hatanaka2013-08-288-2/+90
| | | | | | | | Also, fix predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189432 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Support offsets after segment registersDavid Majnemer2013-08-271-0/+6
| | | | | | | | | | | | | | Summary: MASM let's you do stuff like 'MOV FS:20, EAX' and 'MOV EAX, FS:20' Reviewers: craig.topper, rnk Reviewed By: rnk CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1470 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189407 91177308-0d34-0410-b5e6-96231b3b80d8
* Given target assembler parsers a chance to handle variant expressionsJoerg Sonnenberger2013-08-272-0/+7
| | | | | | | | first. Use this to turn the PPC modifiers into PPC specific expressions, allowing them to work on constants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189400 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add MC support for the new load/store acquire/release instructions.Joey Gouly2013-08-274-0/+131
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189388 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add some negative tests for the recent VFP/NEON instructions.Joey Gouly2013-08-272-3/+108
| | | | | | | Fix two issues I found while writing these tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189341 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix wrong code offset for unwind code SET_FPREG.Kai Nacke2013-08-271-2/+0
| | | | | | | | | | | | | The code offset for unwind code SET_FPREG is wrong because it is set to constant 0. The fix is to do the same as for the other unwind codes: emit a label and later the absolute difference between the label and the begin of the prologue. Also enables the failing test case MC/COFF/seh.s Reviewed by Jim Grosbach, Charles Davis and Nico Rieck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189309 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch implements trap instructions for mips. The test cases are added.Vladimir Medic2013-08-261-2/+58
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189213 91177308-0d34-0410-b5e6-96231b3b80d8
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