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* Fixed disassembler for vstm/vldm ARM VFP instructions.Silviu Baranga2012-05-031-0/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156077 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add missing two-operand VBIC aliases.Jim Grosbach2012-05-021-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156019 91177308-0d34-0410-b5e6-96231b3b80d8
* Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.Richard Barton2012-05-024-29/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155983 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add a few missing add->sub aliases w/ 'w' suffix.Jim Grosbach2012-05-011-0/+12
| | | | | | | | | | | | | | Aliases for adding a negative immediate when using an explicit 'w' suffix. E.g., adds.w r2, #-16 adds.w r2, r2, #-16 addw r2, #-16 addw r2, #-16 addw r2, r2, #-16 rdar://11330769 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155946 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: allow vanilla expressions for movw/movt.Jim Grosbach2012-05-011-0/+5
| | | | | | | | | | Expressions for movw/movt don't always have an :upper16: or :lower16: on them and that's ok. When they don't, it's just a plain [0-65536] immediate result, effectively the same as a :lower16: variant kind. rdar://10550147 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155941 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Unknown assembler directives are now hard errors.Jim Grosbach2012-05-012-3/+3
| | | | | | | | | | | | | | | | Previously, an unsupported/unknown assembler directive issued a warning. That's generally unsafe, and inconsistent with the behaviour of pretty much every system assembler. Now that the MC assemblers are mature enough to be the default on multiple targets, it's reasonable to issue errors for these. For target or platform directives that need to stay warnings, we should add explicit handlers for them in, e.g., ELFAsmParser.cpp, DarwinAsmParser.cpp, et. al., and issue the warning there. rdar://9246275 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155926 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Thumb add(sp plus register) asm constraints.Jim Grosbach2012-04-272-0/+7
| | | | | | | | | | Make sure when parsing the Thumb1 sp+register ADD instruction that the source and destination operands match. In thumb2, just use the wide encoding if they don't. In Thumb1, issue a diagnostic. rdar://11219154 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155748 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM assembly parsing for upper case condition codes on IT instructions.Richard Barton2012-04-271-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155720 91177308-0d34-0410-b5e6-96231b3b80d8
* Missed some register numbers.Benjamin Kramer2012-04-271-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155706 91177308-0d34-0410-b5e6-96231b3b80d8
* Update edis test for r155704.Benjamin Kramer2012-04-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155705 91177308-0d34-0410-b5e6-96231b3b80d8
* Specify cpu to unbreak tests.Evan Cheng2012-04-2616-17/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155604 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: improved assembler diagnostics for missing CPU features.Jim Grosbach2012-04-241-9/+9
| | | | | | | | | | | When an instruction match is found, but the subtarget features it requires are not available (missing floating point unit, or thumb vs arm mode, for example), issue a diagnostic that identifies what the feature mismatch is. rdar://11257547 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155499 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing test cases for ARM VLD3 (single 3-element structure to all lanes)Kevin Enderby2012-04-242-0/+38
| | | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155453 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing test cases for ARM VLD4 (single 4-element structure to all lanes)Kevin Enderby2012-04-242-0/+49
| | | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155444 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add testcases for two-operand variants of VSRA/VRSRA/VSRI.Jim Grosbach2012-04-232-0/+209
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155391 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ARM mode tests for the NEON vector shift-accumulate tests.Jim Grosbach2012-04-231-0/+105
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155390 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Reformat for ease of reading.Jim Grosbach2012-04-231-95/+102
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155389 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Update NEON assembly two-operand aliases.Jim Grosbach2012-04-202-0/+21
| | | | | | | | Use the new TwoOperandAliasConstraint to handle lots of the two-operand aliases for NEON instructions. There's still more to go, but this is a good chunk of them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155210 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM some VFP tblgen'erated two-operand aliases.Jim Grosbach2012-04-201-2/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155178 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Formatting.Jim Grosbach2012-04-201-53/+45
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155177 91177308-0d34-0410-b5e6-96231b3b80d8
* Added support for disassembling unpredictable swp/swpb ARM instructions.Silviu Baranga2012-04-181-0/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155004 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the bahavior of the disassembler when decoding unpredictable mrs ↵Silviu Baranga2012-04-181-0/+18
| | | | | | instructions on ARM. Now the diasassembler emmits warnings instead of errors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155002 91177308-0d34-0410-b5e6-96231b3b80d8
* Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the ↵Silviu Baranga2012-04-182-0/+17
| | | | | | disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155001 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed decoding for the ARM cdp2 instruction. The restriction on the ↵Silviu Baranga2012-04-181-0/+3
| | | | | | coprocessor number was removed for this instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155000 91177308-0d34-0410-b5e6-96231b3b80d8
* Add suport for unpredicatble cases of the cmp, tst, teq and cmnz ARM ↵Silviu Baranga2012-04-181-0/+30
| | | | | | instructions in the disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154999 91177308-0d34-0410-b5e6-96231b3b80d8
* Add disassembler to MIPS. Akira Hatanaka2012-04-178-0/+2042
| | | | | | | | Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154935 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)Kevin Enderby2012-04-172-0/+75
| | | | | | | | instructions with writebacks. And add test a case for all opcodes handed by DecodeVLD2DupInstruction() in ARMDisassembler.cpp . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154884 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM two-operand forms for vhadd and vhsub instructions.Jim Grosbach2012-04-162-0/+53
| | | | | | rdar://11252521 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154875 91177308-0d34-0410-b5e6-96231b3b80d8
* MC assembly parser handling for trailing comma in macro instantiation.Jim Grosbach2012-04-161-0/+24
| | | | | | | | | A trailing comma means no argument at all (i.e., as if the comma were not present), not an empty argument to the invokee. rdar://11252521 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154863 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch fixes 3 problems:Akira Hatanaka2012-04-161-10/+10
| | | | | | | | | | | | | | | 1. CHECKNEXT was used instead of CHECK-NEXT which caused the line to be ignored which in turn hid the next 2 problems: 2. ('sh_offset', 0x{{{[0-9,a-f]+}}) had one too many leading curly braces and failed to do it's job of accepting all hex digits and: 3. The check for the hex values for the code instructions didn't account for blank separators. Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154842 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly two-operand forms for VRSHL.Jim Grosbach2012-04-161-0/+35
| | | | | | rdar://11252521 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154840 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Test formatting.Jim Grosbach2012-04-161-53/+64
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154839 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not add offset in applyFixup. This has already been accounted for in Value. Akira Hatanaka2012-04-161-0/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154838 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM two-operand aliases for VRHADD instructions.Jim Grosbach2012-04-161-0/+27
| | | | | | rdar://11252521 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154832 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Testcase formatting.Jim Grosbach2012-04-161-13/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154831 91177308-0d34-0410-b5e6-96231b3b80d8
* Add -disassemble support for -show-inst and -show-encode capability llvm-mc. ↵Richard Barton2012-04-161-1/+1
| | | | | | | | | Also refactor so all MC paraphernalia are created once for all uses as much as possible. The test change is to account for the fact that the default disassembler behaviour has changed with regards to specifying the assembly syntax to use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154809 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a case of ARM disassembly getting an assert on a bad encodingKevin Enderby2012-04-111-0/+13
| | | | | | | of a VST instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154544 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM 'vuzp.32 Dd, Dm' is a pseudo-instruction.Jim Grosbach2012-04-111-0/+2
| | | | | | | | | | While there is an encoding for it in VUZP, the result of that is undefined, so we should avoid it. Define the instruction as a pseudo for VTRN.32 instead, as the ARM ARM indicates. rdar://11222366 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154511 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM 'vzip.32 Dd, Dm' is a pseudo-instruction.Jim Grosbach2012-04-111-0/+2
| | | | | | | | | | While there is an encoding for it in VZIP, the result of that is undefined, so we should avoid it. Define the instruction as a pseudo for VTRN.32 instead, as the ARM ARM indicates. rdar://11221911 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154505 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up ARM fused multiply + add/sub support some more: rename some iselEvan Cheng2012-04-111-1/+1
| | | | | | | | | | | | predicates. Also remove NEON2 since it's not really useful and it is confusing. If NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it really mean? rdar://10139676 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154480 91177308-0d34-0410-b5e6-96231b3b80d8
* Add retw and lretw instructions. Also, fix Intel syntax parsing for allCharles Davis2012-04-114-0/+31
| | | | | | | ret instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154468 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM disassembly of VLD instructions with writebacks.  And add test a caseKevin Enderby2012-04-112-0/+364
| | | | | | | for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154459 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM add missing Thumb1 two-operand aliases for shift-by-immediate.Jim Grosbach2012-04-111-0/+18
| | | | | | rdar://11222742 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154457 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a number of problems with ARM fused multiply add/subtract instructions.Evan Cheng2012-04-112-0/+87
| | | | | | | | | | | 1. The new instruction itinerary entries are not properly described. 2. The asm parser can't handle vfms and vfnms. 3. There were no assembler, disassembler test cases. 4. HasNEON2 has the wrong assembler predicate. rdar://10139676 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154456 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM fix cc_out operand handling for t2SUBrr instructions.Jim Grosbach2012-04-101-0/+12
| | | | | | | | | | | | We were incorrectly conflating some add variants which don't have a cc_out operand with the mirroring sub encodings, which do. Part of the awesome non-orthogonality legacy of thumb1. Similarly, handling of add/sub of an immediate was sometimes incorrectly removing the cc_out operand for add/sub register variants. rdar://11216577 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154411 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the tests that were supposed to go with r153935 that I forgot svn addCraig Topper2012-04-062-0/+73
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154165 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly aliases for add negative immediates using sub.Jim Grosbach2012-04-051-0/+4
| | | | | | | | | | 'add r2, #-1024' should just use 'sub r2, #1024' rather than erroring out. Thumb1 aliases for adding a negative immediate to the stack pointer, also. rdar://11192734 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154123 91177308-0d34-0410-b5e6-96231b3b80d8
* Added support for unpredictable ADC/SBC instructions on ARM, and also fixed ↵Silviu Baranga2012-04-051-0/+17
| | | | | | some corner cases involving the PC register as an operand for these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154101 91177308-0d34-0410-b5e6-96231b3b80d8
* Added support for handling unpredictable arithmetic instructions on ARM.Silviu Baranga2012-04-052-12/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154100 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly aliases for two-operand V[R]SHR instructions.Jim Grosbach2012-04-051-0/+70
| | | | | | rdar://11189467 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154087 91177308-0d34-0410-b5e6-96231b3b80d8
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