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* CBZ/CBNZ are Thumb2 only. No need for ARM mode tests for them.Jim Grosbach2011-07-281-4/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136408 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for BLX (immediate).Jim Grosbach2011-07-281-1/+3
| | | | | | | | | Add parsing support for BLX (immediate). Since the register operand version is predicated and the label operand version is not, we have to use some special handling to get the operand list right for matching. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136406 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle REG_SEQUENCE with implicitly defined operands.Jakob Stoklund Olesen2011-07-281-0/+21
| | | | | | | | | | | | | Code like that would only be produced by bugpoint, but we should still handle it correctly. When a register is defined by a REG_SEQUENCE of undefs, the register itself is undef. Previously, we would create a register with uses but no defs. Fixes part of PR10520. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136401 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove obsolete FIXME reference in comment.Jim Grosbach2011-07-281-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136400 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for BFC and BFI.Jim Grosbach2011-07-281-2/+24
| | | | | | | | Add parsing support that handles converting the lsb+width source into the odd way we represent the instruction (an inverted bitfield mask). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136399 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM parsing and encoding for ADR.Jim Grosbach2011-07-281-1/+13
| | | | | | | The label does not have a '#' prefix. Add parsing and encoding tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136360 91177308-0d34-0410-b5e6-96231b3b80d8
* Update ARM tests for parsing and encoding of WFE, WFI and YIELD.Jim Grosbach2011-07-282-9/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136358 91177308-0d34-0410-b5e6-96231b3b80d8
* Due to changes coming from the new LLVM type system, you now getDuncan Sands2011-07-281-1/+2
| | | | | | | | bitcasts in this test rather than getelementptr instructions; llvm-gcc produces two bitcasts, clang produces one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136349 91177308-0d34-0410-b5e6-96231b3b80d8
* Add patterns to generate copies for extract_subvector instead ofBruno Cardoso Lopes2011-07-281-3/+3
| | | | | | | using vextractf128. This will reduce the number of issued instruction for several avx codes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136323 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a few patterns to match allzeros without having to use the fp unit.Bruno Cardoso Lopes2011-07-281-1/+1
| | | | | | | Take advantage that the 128-bit vpxor zeros the higher part and use it. This also fixes PR10491 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136321 91177308-0d34-0410-b5e6-96231b3b80d8
* Add SINT_TO_FP and FP_TO_SINT support for v8i32 types. Also moveBruno Cardoso Lopes2011-07-281-0/+14
| | | | | | a convert pattern close to the instruction definition. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136320 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM parsing and encoding tests.Jim Grosbach2011-07-281-0/+112
| | | | | | | UXTAB, UXTAB16, UXTAH, UXTB, UXTB16, and UXTH. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136312 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.Evan Cheng2011-07-273-7/+14
| | | | | | | | | | This can happen in cases where TableGen generated asm matcher cannot check whether a register operand is in the right register class. e.g. mem operands. rdar://8204588 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136292 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for USUB16 and USUB8.Jim Grosbach2011-07-271-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136289 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for USAX.Jim Grosbach2011-07-271-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136288 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix llvm-mc handing of x86 instructions that take 8-bit unsigned immediates.Kevin Enderby2011-07-272-0/+39
| | | | | | | | | | | | | llvm-mc gives an "invalid operand" error for instructions that take an unsigned immediate which have the high bit set such as: pblendw $0xc5, %xmm2, %xmm1 llvm-mc treats all x86 immediates as signed values and range checks them. A small number of x86 instructions use the imm8 field as a set of bits. This change only changes those instructions and where the high bit is not ignored. The others remain unchanged. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136287 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up tabs.Jim Grosbach2011-07-271-16/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136286 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding support for USAT and USAT16.Jim Grosbach2011-07-271-0/+26
| | | | | | | Use range checked immediate operands for instructions. Add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136285 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding tests for USAD8 and USADA8.Jim Grosbach2011-07-271-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136284 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding tests for UQSUB16 and UQSUB8.Jim Grosbach2011-07-271-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136282 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment copy/paste-o.Jim Grosbach2011-07-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136281 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding tests for UQASX and UQSAX.Jim Grosbach2011-07-271-0/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136280 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding tests for UQADD16 and UQADD8.Jim Grosbach2011-07-271-0/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136279 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for UMULL.Jim Grosbach2011-07-271-0/+14
| | | | | | | Fix parsing of the 's' suffix for the mnemonic. Add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136277 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for UMLAL.Jim Grosbach2011-07-271-0/+13
| | | | | | | Fix parsing of the 's' suffix for the mnemonic. Add tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136274 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding tests for UMAAL.Jim Grosbach2011-07-271-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136272 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding tests for UHSUB16 and UHSUB8.Jim Grosbach2011-07-271-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136267 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding tests for UHADD16, UHADD8 and UHASX.Jim Grosbach2011-07-271-0/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136266 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM parsing and encoding of SBFX and UBFX.Jim Grosbach2011-07-272-0/+29
| | | | | | | | | | Encode the width operand as it encodes in the instruction, which simplifies the disassembler and the encoder, by using the imm1_32 operand def. Add a diagnostic for the context-sensitive constraint that the width must be in the range [1,32-lsb]. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding tests for UADD16, UADD8 and UASX.Jim Grosbach2011-07-271-0/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136261 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding tests for TST instruction.Jim Grosbach2011-07-271-0/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136260 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding tests for TEQ instruction.Jim Grosbach2011-07-271-0/+34
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136259 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor the STRT and STRBT instructions to distinguish between the ↵Owen Anderson2011-07-271-0/+1
| | | | | | register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136255 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge the contents from exception-handling-rewrite to the mainline.Bill Wendling2011-07-271-0/+54
| | | | | | | This adds the new instructions 'landingpad' and 'resume'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136253 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for extend instructions.Jim Grosbach2011-07-272-0/+146
| | | | | | | | Assembly parser handling for extend instruction rotate operands. Add tests for the sign extend instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136252 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the ConstantMerge pass about alignment. Fixes PR10514!Nick Lewycky2011-07-271-2/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136250 91177308-0d34-0410-b5e6-96231b3b80d8
* The vpermilps and vpermilpd have different behaviour regarding theBruno Cardoso Lopes2011-07-271-0/+16
| | | | | | | | | usage of the shuffle bitmask. Both work in 128-bit lanes without crossing, but in the former the mask of the high part is the same used by the low part while in the later both lanes have independent masks. Handle this properly and and add support for vpermilpd. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136200 91177308-0d34-0410-b5e6-96231b3b80d8
* It is quiet possible that inlined function body is split into multiple ↵Devang Patel2011-07-271-0/+140
| | | | | | chunks of consequtive instructions. But, there is not any way to describe this in .debug_inline accelerator table used by gdb. However, describe non contiguous ranges of inlined function body appropriately using AT_range of DW_TAG_inlined_subroutine debug info entry. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136196 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove these two directories. The tests can be ported to dragonegg ifEric Christopher2011-07-2737-328/+0
| | | | | | | they're still wanted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136193 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove test/FrontendC, almost all of the tests have been migratedEric Christopher2011-07-26362-5534/+0
| | | | | | | to clang now, the rest are in process (6) or have been deleted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136191 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate copies of undefined values during coalescing.Jakob Stoklund Olesen2011-07-261-0/+27
| | | | | | | | | | These copies would coalesce easily, but the resulting value would be defined by a deleted instruction. Now we also remove the undefined value number from the destination register. This fixes PR10503. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136174 91177308-0d34-0410-b5e6-96231b3b80d8
* Update test.Benjamin Kramer2011-07-261-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136170 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a neat little two's complement hack for x86.Benjamin Kramer2011-07-261-0/+11
| | | | | | | | | | On x86 we can't encode an immediate LHS of a sub directly. If the RHS comes from a XOR with a constant we can fold the negation into the xor and add one to the immediate of the sub. Then we can turn the sub into an add, which can be commuted and encoded efficiently. This code is generated for __builtin_clz and friends. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136167 91177308-0d34-0410-b5e6-96231b3b80d8
* Recognize unpckh* masks and match 256-bit versions. The new versions areBruno Cardoso Lopes2011-07-266-85/+58
| | | | | | | different from the previous 128-bit because they work in lanes. Update a few comments and add testcases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136157 91177308-0d34-0410-b5e6-96231b3b80d8
* Prevent x86-specific DAGCombine from creating nodes with illegal type (which ↵Eli Friedman2011-07-261-2/+1
| | | | | | could not be selected). Fixes a minor isel issue that was breaking the testcase from r136130. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136148 91177308-0d34-0410-b5e6-96231b3b80d8
* FileCheck'ize test.Jim Grosbach2011-07-261-20/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136135 91177308-0d34-0410-b5e6-96231b3b80d8
* XFAIL this test while I investigate it; it's failing for an unexpected reason.Eli Friedman2011-07-261-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136131 91177308-0d34-0410-b5e6-96231b3b80d8
* Add obvious missing case to switch. PR10497.Eli Friedman2011-07-261-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136130 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM diagnostics for ldrexd/stredx out of order paired register operands.Jim Grosbach2011-07-261-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136110 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM parsing and encoding tests for load/store exclusive instructions.Jim Grosbach2011-07-262-24/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136105 91177308-0d34-0410-b5e6-96231b3b80d8
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