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* Force a CPU on test so it doesn't depend on microarchitectural scheduling ↵Benjamin Kramer2013-10-121-2/+2
| | | | | | decisions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192532 91177308-0d34-0410-b5e6-96231b3b80d8
* For Mips16, start to consolidate all forms of 32 bit literal loading so thatReed Kotler2013-10-121-6/+13
| | | | | | | | they can be better handled and optimized in the Mips16 constant island code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192520 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixing problems in lli's RemoteMemoryManager.Andrew Kaylor2013-10-112-2/+4
| | | | | | | | | | This fixes a problem from a previous check-in where a return value was omitted. Previously the remote/stubs-remote.ll and remote/stubs-sm-pic.ll tests were reporting passes, but they should have been failing. Those tests attempt to link against an external symbol and remote symbol resolution is not supported. The old RemoteMemoryManager implementation resulted in local symbols being used for resolution and the child process crashed but the test didn't notice. With this check-in remote symbol resolution fails, and so the test (correctly) fails. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192514 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding multiple object support to MCJIT EH frame handlingAndrew Kaylor2013-10-112-0/+65
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192504 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add scalar i32 add testMatt Arsenault2013-10-111-0/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192501 91177308-0d34-0410-b5e6-96231b3b80d8
* Use CHECK-LABELMatt Arsenault2013-10-111-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192500 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips: Disassemble sign-extended 64 bit immediates properly.Benjamin Kramer2013-10-111-0/+3
| | | | | | This doesn't change the meaning of the output, but makes look right. PR17539. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192483 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove kill flags after if conversion if necessaryMatthias Braun2013-10-111-0/+30
| | | | | | | | | | | | | | | | | | | When if converting something like: true: ... = R0<kill> false: ... = R0<kill> then the instructions of the true block must not have a <kill> flag anymore, as the instruction of the false block follow and do still read the R0 value. Specifically this patch determines the set of register live-in in the false block (possibly after simulating the liveness changes of the duplicated instructions). Each of these live-in registers mustn't be killed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192482 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] Load slicing test case: attempt to really fix the buildbots ↵Quentin Colombet2013-10-111-2/+2
| | | | | | | | | (used sse4.2 instead of avx!). <rdar://problem/14477220> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192480 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info Testing Case: check for the name of a structure.Manman Ren2013-10-111-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192478 91177308-0d34-0410-b5e6-96231b3b80d8
* Really fix CHECK-LABEL and CHECK-DAG interaction. This actually just ↵Stephen Lin2013-10-111-0/+11
| | | | | | restores the initial implementation that was in r186162 but got lost in some subsequent refactoring. More explicit variable names and comments are present now to hopefully prevent repeat regression, as well as another test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192477 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] Reapply load slicing (192471) with a test that explicitly set ↵Quentin Colombet2013-10-111-0/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sse4.2 support. This should fix the buildbots. Original commit message: [DAGCombiner] Slice a big load in two loads when the element are next to each other in memory and the target has paired load and performs post-isel loads combining. E.g., this optimization will transform something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and performs post-isel loads combining. One should overload TargetLowering::hasPairedLoad to provide this information. The default is false. <rdar://problem/14477220> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192476 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] Revert load slicing (r192471), until I figure out why it fails ↵Quentin Colombet2013-10-111-140/+0
| | | | | | on ubuntu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192474 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Tests: Be less dependent on a specific schedule/regalloc"Matthias Braun2013-10-1110-53/+55
| | | | | | | | | This reverts r192454 Apparently FileCheck isn't as smart as I though and does not enforce a topological order between variable defs+uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192472 91177308-0d34-0410-b5e6-96231b3b80d8
* [DAGCombiner] Slice a big load in two loads when the element are next to eachQuentin Colombet2013-10-111-0/+140
| | | | | | | | | | | | | | | | | | | | | | | | | other in memory and the target has paired load and performs post-isel loads combining. E.g., this optimization will transform something like this: a = load i64* addr b = trunc i64 a to i32 c = lshr i64 a, 32 d = trunc i64 c to i32 into: b = load i32* addr1 d = load i32* addr2 Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and performs post-isel loads combining. One should overload TargetLowering::hasPairedLoad to provide this information. The default is false. <rdar://problem/14477220> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192471 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix handling of CHECK-DAG inside of CHECK-LABEL.Rafael Espindola2013-10-111-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192463 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Fix FP ABI attributes with no VFP enabled.Amara Emerson2013-10-113-12/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192458 91177308-0d34-0410-b5e6-96231b3b80d8
* Tests: Be less dependent on a specific schedule/regallocMatthias Braun2013-10-1110-55/+53
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192454 91177308-0d34-0410-b5e6-96231b3b80d8
* This reverts 192447 because of compiler warning generated on darwin build.Matheus Almeida2013-10-111-15/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192451 91177308-0d34-0410-b5e6-96231b3b80d8
* This reverts r192449 because of compiler warning generated on darwin build.Matheus Almeida2013-10-111-48/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192450 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Direct Object Emission for the majority of the ELM instructions.Matheus Almeida2013-10-111-0/+48
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192449 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction.Matheus Almeida2013-10-111-0/+15
| | | | | | | | | | INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. This happens because MSA registers may be suffixed by an index in the form of an immediate or a general purpose register. The changes to parseMSARegs reflect that requirement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192447 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Improves robustness of the test by enhancing pattern matching.Matheus Almeida2013-10-111-240/+360
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192446 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Switch from StrongPHIElimination to PHIElimination in ↵Justin Holewinski2013-10-111-0/+38
| | | | | | | | NVPTXTargetMachine, and add some missing optimization passes to addOptimizedRegAlloc Fixes PR17529 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192445 91177308-0d34-0410-b5e6-96231b3b80d8
* Make AsmPrinter::emitImplicitDef a virtual method so targets can emit custom ↵Justin Holewinski2013-10-111-0/+9
| | | | | | | | | | | | | comments for implicit defs For NVPTX, this fixes a crash where the emitImplicitDef implementation was expecting physical registers, while NVPTX uses virtual registers (with a couple of exceptions). Now, the implicit def comment will be emitted as a true PTX register name. Other targets can use this to customize the output of implicit def comments. Fixes PR17519 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192444 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Add a test case for disabled neon/fpu features.Amara Emerson2013-10-111-0/+33
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192440 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from ↵Daniel Sanders2013-10-111-0/+160
| | | | | | normal IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192438 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not ↵Daniel Sanders2013-10-111-0/+40
| | | | | | intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192435 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target fix bug in emitArrayBound() causing segmentation faultRobert Lytton2013-10-112-1/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192434 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target does not emit '.hidden' or '.protected' attributesRobert Lytton2013-10-111-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192433 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: fix bug in XCoreLowerThreadLocal.cppRobert Lytton2013-10-111-0/+39
| | | | | | | | | When a ConstantExpr which uses a thread local is part of a PHI node instruction, the insruction that replaces the ConstantExpr must be inserted in the predecessor block, in front of the terminator instruction. If the predecessor block has multiple successors, the edge is first split. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192432 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: add XCoreTargetLowering::isZExtFree()Robert Lytton2013-10-111-0/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192431 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching fmadd.[wd] from normal IR (i.e. not ↵Daniel Sanders2013-10-111-0/+44
| | | | | | intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192430 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] ↵Daniel Sanders2013-10-111-0/+112
| | | | | | from normal IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192429 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement aarch64 neon instruction set AdvSIMD (copy).Kevin Qin2013-10-113-0/+411
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192410 91177308-0d34-0410-b5e6-96231b3b80d8
* Tests: Do not unnecessarily depend on kill commentsMatthias Braun2013-10-101-9/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192404 91177308-0d34-0410-b5e6-96231b3b80d8
* Tests: Use CHECK-LABEL where possibleMatthias Braun2013-10-104-15/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192403 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: In DIBuilder, the context field of subprogram is updated to useManman Ren2013-10-101-1/+8
| | | | | | | | | DIScopeRef. A paired commit at clang is required due to changes to DIBuilder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192378 91177308-0d34-0410-b5e6-96231b3b80d8
* Add comments to debug info testing case.Manman Ren2013-10-101-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192376 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix trunc i64 to i32 on SIMatt Arsenault2013-10-101-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192375 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use -verify-machineinstrs for most testsTom Stellard2013-10-1084-86/+86
| | | | | | | | | | | We can't enable the verifier for tests with SI_IF and SI_ELSE, because these instructions are always followed by a COPY which copies their result to the next basic block. This violates the machine verifier's rule that non-terminators can not folow terminators. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192366 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-103-0/+1912
| | | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192361 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Implement AArch64 vector load/store multiple N-element structure ↵Rafael Espindola2013-10-103-1912/+0
| | | | | | | | class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)." This reverts commit r192352. It broke the build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192354 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement AArch64 vector load/store multiple N-element structure class ↵Hao Liu2013-10-103-0/+1912
| | | | | | | | | | | | | | SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192352 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable function padding to get this test to pass on atom.Benjamin Kramer2013-10-101-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192348 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: correct liveness flags during ARMLoadStoreOptTim Northover2013-10-101-0/+40
| | | | | | | | | | | | | | | | | | | | | | When we had a sequence like: s1 = VLDRS [r0, 1], Q0<imp-def> s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def> s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def> s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def> we were gathering the {s0, s1} loads below the s3 load. This is fine, but confused the verifier since now the s3 load had Q0<imp-use> with no definition above it. This should mark such uses <undef> as well. The liveness structure at the beginning and end of the block is unaffected, and the true sN definitions should prevent any dodgy reorderings being introduced elsewhere. rdar://problem/15124449 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192344 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow non-AVX form of pmovmskb to take a GR64 operand.Craig Topper2013-10-101-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192341 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Do not generate INS/EXT nodes if target does not have support forAkira Hatanaka2013-10-091-3/+6
| | | | | | | | ins/ext. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192330 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: In DIBuilder, the context and type fields of template_type andManman Ren2013-10-091-39/+60
| | | | | | | | | template_value are updated to use DIRef. A paired commit at clang is required due to changes to DIBuilder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192320 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: In DIBuilder, the context field of a forward decl is updatedManman Ren2013-10-091-34/+46
| | | | | | | to use DIScopeRef. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192309 91177308-0d34-0410-b5e6-96231b3b80d8
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