| Commit message (Collapse) | Author | Age | Files | Lines |
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r195424 | haoliu | 2013-11-22 00:47:22 -0800 (Fri, 22 Nov 2013) | 4 lines
Fix the bugs about AArch64 Load/Store vector types and bitcast between i64 and vector types.
e.g. "%tmp = load <2 x i64>* %ptr" can't be selected.
"%tmp = bitcast i64 %in to <2 x i32>" can't be selected.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195764 91177308-0d34-0410-b5e6-96231b3b80d8
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r195408 | jiangning | 2013-11-21 18:45:13 -0800 (Thu, 21 Nov 2013) | 2 lines
For AArch64 back-end instruction selection, lower Neon_Lowxxx with EXTRCT_SUBREG.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195762 91177308-0d34-0410-b5e6-96231b3b80d8
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r195713 | kevinqin | 2013-11-25 18:33:42 -0800 (Mon, 25 Nov 2013) | 1 line
[AArch64]Implement 128 bit register copy with NEON.
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r195682 | rafael | 2013-11-25 12:46:18 -0800 (Mon, 25 Nov 2013) | 1 line
Use -triple to fix the test on non-ELF hosts.
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r195469 | dsanders | 2013-11-22 07:47:18 -0800 (Fri, 22 Nov 2013) | 4 lines
[mips][msa] Add test case that should have been added in r195456.
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r195444 | dsanders | 2013-11-22 03:24:50 -0800 (Fri, 22 Nov 2013) | 4 lines
[mips][msa] Float vector constants cannot use ldi.[wd] directly. Bitcast from the appropriate integer vector type.
Fixes an instruction selection failure detected by llvm-stress.
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r195364 | dsanders | 2013-11-21 08:11:31 -0800 (Thu, 21 Nov 2013) | 12 lines
[mips][msa] Fix a corner case in performORCombine() when combining nodes into VSELECT.
Mask == ~InvMask asserts if the width of Mask and InvMask differ.
The combine isn't valid (with two exceptions, see below) if the widths differ
so test for this before testing Mask == ~InvMask.
In the specific cases of Mask=~0 and InvMask=0, as well as Mask=0 and
InvMask=~0, the combine is still valid. However, there are more appropriate
combines that could be used in these cases such as folding x & 0 to 0, or
x & ~0 to x.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195741 91177308-0d34-0410-b5e6-96231b3b80d8
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r195343 | dsanders | 2013-11-21 03:40:14 -0800 (Thu, 21 Nov 2013) | 5 lines
[mips][msa/dsp] Only do DSP combines if DSP is enabled.
Fixes a crash (null pointer dereferenced) when MSA is enabled.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195740 91177308-0d34-0410-b5e6-96231b3b80d8
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r195731 | rsandifo | 2013-11-26 10:53:16 +0000 (Tue, 26 Nov 2013) | 7 lines
[SystemZ] Fix incorrect use of RISBG for a zero-extended right shift
We would wrongly transform the testcase into the equivalent of an AND with 1.
The problem was that, when testing whether the shifted-in bits of the right
shift were significant, we used the width of the final zero-extended result
rather than the width of the shifted value.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195736 91177308-0d34-0410-b5e6-96231b3b80d8
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r195716 | kevinqin | 2013-11-25 19:26:47 -0800 (Mon, 25 Nov 2013) | 3 lines
Refactored the implementation of AArch64 NEON instruction ZIP, UZP
and TRN.
Fix a bug when mixed use of vget_high_u8() and vuzp_u8().
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195735 91177308-0d34-0410-b5e6-96231b3b80d8
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r195679 | rafael | 2013-11-25 12:15:14 -0800 (Mon, 25 Nov 2013) | 12 lines
Don't use nopl in cpus that don't support it.
Patch by Mikulas Patocka. I added the test. I checked that for cpu names that
gas knows about, it also doesn't generate nopl.
The modified cpus:
i686 - there are i686-class CPUs that don't have nopl: Via c3, Transmeta
Crusoe, Microsoft VirtualBox - see
https://bbs.archlinux.org/viewtopic.php?pid=775414
k6, k6-2, k6-3, winchip-c6, winchip2 - these are 586-class CPUs
via c3 c3-2 - see https://bugs.archlinux.org/task/19733 as a proof that
Via c3 and c3-Nehemiah don't have nopl
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195730 91177308-0d34-0410-b5e6-96231b3b80d8
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r195670 | void | 2013-11-25 10:05:22 -0800 (Mon, 25 Nov 2013) | 5 lines
Unrevert r195599 with testcase fix.
I'm not sure how it was checking for the wrong values...
PR18023.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195672 91177308-0d34-0410-b5e6-96231b3b80d8
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r195636 | aemerson | 2013-11-25 03:24:18 -0800 (Mon, 25 Nov 2013) | 2 lines
Revert r195599 as it broke the builds.
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r195635 | dsanders | 2013-11-25 11:14:43 +0000 (Mon, 25 Nov 2013) | 19 lines
Fixed tryFoldToZero() for vector types that need expansion.
Summary:
Moved the requirement for SelectionDAG::getConstant() to return legally
typed nodes slightly earlier. There were two optional DAGCombine passes
that were missed out and were required to produce type-legal DAGs.
Simplified a code-path in tryFoldToZero() to use SelectionDAG::getConstant().
This provides support for both promoted and expanded vector types whereas the
previous code only supported promoted vector types.
Fixes a "Type for zero vector elements is not legal" assertion detected by
an llvm-stress generated test.
Reviewers: resistor
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D2251
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195651 91177308-0d34-0410-b5e6-96231b3b80d8
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r195591 | haoliu | 2013-11-24 17:53:26 -0800 (Sun, 24 Nov 2013) | 5 lines
Fixed a bug about disassembling AArch64 post-index load/store single element instructions.
ie. echo "0x00 0x04 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
echo "0x00 0x00 0x80 0x0d" | ../bin/llvm-mc -triple=aarch64 -mattr=+neon -disassemble
will be disassembled into the same instruction st1 {v0b}[0], [x0], x0.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195619 91177308-0d34-0410-b5e6-96231b3b80d8
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r195330 | apazos | 2013-11-21 00:16:15 -0800 (Thu, 21 Nov 2013) | 5 lines
Implemented Neon scalar vdup_lane intrinsics.
Fixed scalar dup alias and added test case.
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r195327 | apazos | 2013-11-20 23:37:04 -0800 (Wed, 20 Nov 2013) | 6 lines
Implemented Neon scalar by element intrinsics.
Intrinsics implemented: vqdmull_lane, vqdmulh_lane, vqrdmulh_lane,
vqdmlal_lane, vqdmlsl_lane scalar Neon intrinsics.
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r195514 | tstellar | 2013-11-22 15:07:58 -0800 (Fri, 22 Nov 2013) | 6 lines
R600/SI: Fixing handling of condition codes
We were ignoring the ordered/onordered bits and also the signed/unsigned
bits of condition codes when lowering the DAG to MachineInstrs.
NOTE: This is a candidate for the 3.4 branch.
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r195493 | arsenm | 2013-11-22 11:24:39 -0800 (Fri, 22 Nov 2013) | 6 lines
StructurizeCFG: Fix verification failure with some loops.
If the beginning of the loop was also the entry block
of the function, branches were inserted to the entry block
which isn't allowed. If this occurs, create a new dummy
function entry block that branches to the start of the loop.
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r195492 | arsenm | 2013-11-22 11:24:37 -0800 (Fri, 22 Nov 2013) | 1 line
StructurizeCFG: Fix inverting a branch on an argument
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r195491 | probinson | 2013-11-22 11:11:24 -0800 (Fri, 22 Nov 2013) | 11 lines
Teach ISel not to optimize 'optnone' functions (revised).
Improvements over r195317:
- Set/restore EnableFastISel flag instead of just running FastISel within
SelectAllBasicBlocks; the flag is checked in various places, and
FastISel won't run properly if those places don't do the right thing.
- Test looks for normal ISel versus FastISel behavior, and not
something more subtle that doesn't work everywhere.
Based on work by Andrea Di Biagio.
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r195477 | rafael | 2013-11-22 09:58:12 -0800 (Fri, 22 Nov 2013) | 13 lines
Add a fixed version of r195470 back.
The fix is simply to use CurI instead of I when handling aliases to
avoid accessing a invalid iterator.
original message:
Convert linkonce* to weak* instead of strong.
Also refactor the logic into a helper function. This is an important improve
on mingw where the linker complains about mixed weak and strong symbols.
Converting to weak ensures that the symbol is not dropped, but keeps in a
comdat, making the linker happy.
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r195476 | hliao | 2013-11-22 09:56:57 -0800 (Fri, 22 Nov 2013) | 6 lines
Fix PR18014
- When simplifying the mask generation for BLEND, check whether that mask is
also consumed by other non-BLEND insns. If true, skip that simplification.
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r195599 | void | 2013-11-24 21:01:21 -0800 (Sun, 24 Nov 2013) | 4 lines
Don't look past volatile loads.
A volatile load should block us from trying to coalesce stores.
PR18023
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r195439 | kcc | 2013-11-22 02:30:39 -0800 (Fri, 22 Nov 2013) | 3 lines
Revert r195318 as it causes miscompilation (PR18029)
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r195473 | rsandifo | 2013-11-22 17:28:28 +0000 (Fri, 22 Nov 2013) | 10 lines
[SystemZ] Fix TMHH and TMHL usage for z10 with -O0
I've no idea why I decided to handle TMxx differently from all the other
high/low logic operations, but it was a stupid thing to do. The high
registers aren't available as separate 32-bit registers on z10,
so subreg_h32 can't be used on a GR64 there.
I've normally been testing with z196 and with -O3 and so hadn't noticed
this until now.
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r195398 | tstellar | 2013-11-21 16:41:05 -0800 (Thu, 21 Nov 2013) | 7 lines
SelectionDAG: Optimize expansion of vec_type = BITCAST scalar_type
The legalizer can now do this type of expansion for more
type combinations without loading and storing to and
from the stack.
NOTE: This is a candidate for the 3.4 branch.
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r195339 | chapuni | 2013-11-21 02:55:15 -0800 (Thu, 21 Nov 2013) | 5 lines
Revert r195317 (and r195333), "Teach ISel not to optimize 'optnone' functions."
It broke, at least, i686 target. It is reproducible with "llc -mtriple=i686-unknown".
FYI, it didn't appear to add either "-O0" or "-fast-isel".
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r195333 | kcc | 2013-11-21 01:28:16 -0800 (Thu, 21 Nov 2013) | 1 line
add 'REQUIRES: asserts' to a test that uses 'llc -debug'; this fixes the no-asserts build
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r195355 | dsanders | 2013-11-21 13:24:49 +0000 (Thu, 21 Nov 2013) | 20 lines
Add support for legalizing SETNE/SETEQ by inverting the condition code and the result of the comparison.
Summary:
LegalizeSetCCCondCode can now legalize SETEQ and SETNE by returning the inverse
condition and requesting that the caller invert the result of the condition.
The caller of LegalizeSetCCCondCode must handle the inverted CC, and they do
so as follows:
SETCC, BR_CC:
Invert the result of the SETCC with SelectionDAG::getNOT()
SELECT_CC:
Swap the true/false operands.
This is necessary for MSA which lacks an integer SETNE instruction.
Reviewers: resistor
CC: llvm-commits
Differential Revision: http://llvm-reviews.chandlerc.com/D2229
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r195317 | probinson | 2013-11-20 22:33:32 -0800 (Wed, 20 Nov 2013) | 4 lines
Teach ISel not to optimize 'optnone' functions.
Based on work by Andrea Di Biagio.
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r195272 | hfinkel | 2013-11-20 12:54:55 -0800 (Wed, 20 Nov 2013) | 4 lines
PPC popcnt[dw] do not have record forms
The instruction definitions incorrectly specified that popcntd and popcntw have
record forms; they do not. This mistake was causing invalid code generation.
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r195318 | void | 2013-11-20 23:04:30 -0800 (Wed, 20 Nov 2013) | 29 lines
The basic problem is that some mainstream programs cannot deal with the way
clang optimizes tail calls, as in this example:
int foo(void);
int bar(void) {
return foo();
}
where the call is transformed to:
calll .L0$pb
.L0$pb:
popl %eax
.Ltmp0:
addl $_GLOBAL_OFFSET_TABLE_+(.Ltmp0-.L0$pb), %eax
movl foo@GOT(%eax), %eax
popl %ebp
jmpl *%eax # TAILCALL
However, the GOT references must all be resolved at dlopen() time, and so this
approach cannot be used with lazy dynamic linking (e.g. using RTLD_LAZY), which
usually populates the PLT with stubs that perform the actual resolving.
This patch changes X86TargetLowering::LowerCall() to skip tail call
optimization, if the called function is a global or external symbol.
Patch by Dimitry Andric!
PR15086
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r195157 | petarj | 2013-11-19 22:56:00 +0100 (Tue, 19 Nov 2013) | 8 lines
[mips] Resolve relocation for the stubs in MCJIT when load address is known
Instead of processing relocation for branch to stubs right away, emit a
modified relocation and add it to queue to be resolved later when final load
address is known.
This resolves seven MIPS MCJIT issues that were caused by missing relocation
fixups at the end.
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r195162 | arnolds | 2013-11-19 14:20:20 -0800 (Tue, 19 Nov 2013) | 12 lines
SLPVectorizer: Fix stale for Value pointer array
We are slicing an array of Value pointers and process those slices in a loop.
The problem is that we might invalidate a later slice by vectorizing a former
slice.
Use a WeakVH to track the pointer. If the pointer is deleted or RAUW'ed we can
tell.
The test case will only fail when running with libgmalloc.
radar://15498655
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r195152 | jacksprat | 2013-11-19 12:53:28 -0800 (Tue, 19 Nov 2013) | 1 line
reverts 195057 per request
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r195129 | mcinally | 2013-11-19 06:36:00 -0800 (Tue, 19 Nov 2013) | 2 lines
Fix assembly operands for the SSE2 cvtsd2ss instruction.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195218 91177308-0d34-0410-b5e6-96231b3b80d8
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r195118 | chandlerc | 2013-11-19 01:03:18 -0800 (Tue, 19 Nov 2013) | 22 lines
Fix an issue where SROA computed different results based on the relative
order of slices of the alloca which have exactly the same size and other
properties. This was found by a perniciously unstable sort
implementation used to flush out buggy uses of the algorithm.
The fundamental idea is that findCommonType should return the best
common type it can find across all of the slices in the range. There
were two bugs here previously:
1) We would accept an integer type smaller than a byte-width multiple,
and if there were different bit-width integer types, we would accept
the first one. This caused an actual failure in the testcase updated
here when the sort order changed.
2) If we found a bad combination of types or a non-load, non-store use
before an integer typed load or store we would bail, but if we found
the integere typed load or store, we would use it. The correct
behavior is to always use an integer typed operation which covers the
partition if one exists.
While a clever debugging sort algorithm found problem #1 in our existing
test cases, I have no useful test case ideas for #2. I spotted in by
inspection when looking at this code.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195217 91177308-0d34-0410-b5e6-96231b3b80d8
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r195100 | djasper | 2013-11-18 20:26:05 -0800 (Mon, 18 Nov 2013) | 6 lines
Add .clang-format without column limit to subdirectory tests/.
A column limit in the test folder can lead to trouble as the RUN, CHECK,
etc. comments can potentially be broken over multiple lines changing
their meaning. Without column limit, clang-format will simply keep the
test author's line breaks.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195114 91177308-0d34-0410-b5e6-96231b3b80d8
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r195094 | atrick | 2013-11-18 19:29:59 -0800 (Mon, 18 Nov 2013) | 3 lines
Use symbolic operands in the patchpoint folding routine and fix a spilling bug.
Fixes <rdar://15487687> [JS] AnyRegCC argument ends up being spilled
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195113 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195078 91177308-0d34-0410-b5e6-96231b3b80d8
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integer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195072 91177308-0d34-0410-b5e6-96231b3b80d8
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195071 91177308-0d34-0410-b5e6-96231b3b80d8
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No true functional changes.
Change the "hack" name of emitMipsHackSTOCG to emitSymSTO.
Remove demonstration code in AsmParser for emitMipsHackSTOCG and
emitMipsHackELFFlags. The STO field is in an ELF symbol and is not
an explicit directive. That said, we are missing the compliment call
in AsmParser and that will need to be addressed soon.
XFAIL dummy tests for emitMipsHackELFFlags and emitMipsHackELFFlags.
These will built out with following patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195067 91177308-0d34-0410-b5e6-96231b3b80d8
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-debug-dump
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195063 91177308-0d34-0410-b5e6-96231b3b80d8
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This reverts commit r190888, to fix PR17967. The original change wasn't
the right way to get @feat.00 into the object file. The right fix is to
make @feat.00 be a global symbol.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195053 91177308-0d34-0410-b5e6-96231b3b80d8
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lowering only for load/stores to scalar allocas. The resulting values
confuse the backend and don't add anything because we can describe
array-allocas with a dbg.declare intrinsic just fine.
rdar://problem/15464571
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195052 91177308-0d34-0410-b5e6-96231b3b80d8
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(except functions marked always_inline).
Functions with 'optnone' must also have 'noinline' so they don't get
inlined into any other function.
Based on work by Andrea Di Biagio.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195046 91177308-0d34-0410-b5e6-96231b3b80d8
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