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* LoopVectorizer: Only allow vectorization of intrinsics. We can't know for ↵Nadav Rotem2013-09-211-3/+28
| | | | | | | | | | sure that the functions 'abs' or 'round' are the functions from libm. rdar://15012650 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191122 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "SLPVectorizer: Handle more horizontal reductions (disabled)"Arnold Schwaighofer2013-09-211-415/+0
| | | | | | | | | This reverts commit r191108. The horizontal.ll test case fails under libgmalloc. Thanks Shuxin for pointing this out to me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191121 91177308-0d34-0410-b5e6-96231b3b80d8
* Move emission of the debug string table to early in the debugEric Christopher2013-09-203-13/+13
| | | | | | | info finalization to greatly reduce the number of fixups that the assembler has to handle in order to improve compile time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191119 91177308-0d34-0410-b5e6-96231b3b80d8
* Resurrect r191017 " GVN proceeds in the presence of dead code" plus a fix to ↵Shuxin Yang2013-09-208-22/+220
| | | | | | | | | | PR17307 & 17308. The problem of r191017 is that when GVN fabricate a val-number for a dead instruction (in order to make following expr-PRE happy), it forget to fabricate a leader-table entry for it as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191118 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some more MCJIT PIC test XFAILs (for i386)Andrew Kaylor2013-09-205-5/+5
| | | | | | Patch by Dimitry Andric git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191111 91177308-0d34-0410-b5e6-96231b3b80d8
* SLPVectorizer: Handle more horizontal reductions (disabled)Arnold Schwaighofer2013-09-201-0/+415
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Match reductions starting at binary operation feeding into a phi. The code handles trees like r += v1 + v2 + v3 ... and r += v1 r += v2 ... and r *= v1 + v2 + ... We currently only handle associative operations (add, fadd fast). The code can now also handle reductions feeding into stores. a[i] = v1 + v2 + v3 + ... The code is currently disabled behind the flag "-slp-vectorize-hor". The cost model for most architectures is not there yet. I found one opportunity of a horizontal reduction feeding a phi in TSVC (LoopRerolling-flt) and there are several opportunities where reductions feed into stores. radar://14607682 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191108 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete empty files.Joerg Sonnenberger2013-09-202-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191105 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r191017, it results in segmentation faults in Qt.Joerg Sonnenberger2013-09-208-220/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191104 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Canonicalize (gep i8* X, -(ptrtoint Y)) to (sub (ptrtoint X), ↵Benjamin Kramer2013-09-201-0/+14
| | | | | | | | | | (ptrtoint Y)) The GEP pattern is what SCEV expander emits for "ugly geps". The latter is what you get for pointer subtraction in C code. The rest of instcombine already knows how to deal with that so just canonicalize on that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191090 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test: Mark 3 tests as XFAIL:msvc.NAKAMURA Takumi2013-09-203-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191087 91177308-0d34-0410-b5e6-96231b3b80d8
* test/tools/lto/lit.local.cfg: Suppress llvm-lto test on Cygwin and Win32, ↵NAKAMURA Takumi2013-09-201-0/+3
| | | | | | for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191086 91177308-0d34-0410-b5e6-96231b3b80d8
* Move x86-dependent tests into the right directory.Benjamin Kramer2013-09-202-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191082 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: constrain gnu pubnames test furtherDavid Blaikie2013-09-191-10/+32
| | | | | | | | | | Ensures that the pubnames entries actually refer to the intended entities. This test could be more flexible if there was a way to do multiline FileCheck matches with captures (in that way the test wouldn't need to have hardcoded offset values and would thus be resilient to changes in the layout of the DIEs in this CU). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191055 91177308-0d34-0410-b5e6-96231b3b80d8
* Added support for generate DWARF .debug_aranges sections automatically.Richard Mitton2013-09-192-0/+159
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191052 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: llvm-dwarfdump support for gnu_pubnames sectionDavid Blaikie2013-09-191-13/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191050 91177308-0d34-0410-b5e6-96231b3b80d8
* PR16726: extend rol/ror matchingKai Nacke2013-09-191-0/+76
| | | | | | | | | | | | | | | | | | | | | | C-like languages promote types like unsigned short to unsigned int before performing an arithmetic operation. Currently the rotate matcher in the DAGCombiner does not consider this situation. This commit extends the DAGCombiner in the way that the pattern (or (shl ([az]ext x), (*ext y)), (srl ([az]ext x), (*ext (sub 32, y)))) is folded into ([az]ext (rotl x, y)) The matching is restricted to aext and zext because in this cases the upper bits are either undefined or known. Test case is included. This fixes PR16726. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191049 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert PR16726: extend rol/ror matchingKai Nacke2013-09-191-76/+0
| | | | | | There is a buildbot failure. Need to investigate this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191048 91177308-0d34-0410-b5e6-96231b3b80d8
* PR16726: extend rol/ror matchingKai Nacke2013-09-191-0/+76
| | | | | | | | | | | | | | | | | | | | | | C-like languages promote types like unsigned short to unsigned int before performing an arithmetic operation. Currently the rotate matcher in the DAGCombiner does not consider this situation. This commit extends the DAGCombiner in the way that the pattern (or (shl ([az]ext x), (*ext y)), (srl ([az]ext x), (*ext (sub 32, y)))) is folded into ([az]ext (rotl x, y)) The matching is restricted to aext and zext because in this cases the upper bits are either undefined or known. Test case is included. This fixes PR16726. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191045 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: Improve IR annotation comments for GNU pubthings.David Blaikie2013-09-191-11/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191043 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix LTO handling of module-level assembly (PR14152).Peter Collingbourne2013-09-196-13/+27
| | | | | | Patch by Tom Roeder! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191042 91177308-0d34-0410-b5e6-96231b3b80d8
* Add testcase to make sure we don't generate too many jumps for a une compare.Bill Wendling2013-09-191-0/+43
| | | | | | | <rdar://problem/7859988> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191040 91177308-0d34-0410-b5e6-96231b3b80d8
* [Fast-math] Disable "(C1/X)*C2 => (C1*C2)/X" if C1/X has multiple uses.Shuxin Yang2013-09-191-0/+12
| | | | | | | | | | | | | | | | | | | If "C1/X" were having multiple uses, the only benefit of this transformation is to potentially shorten critical path. But it is at the cost of instroducing additional div. The additional div may or may not incur cost depending on how div is implemented. If it is implemented using Newton–Raphson iteration, it dosen't seem to incur any cost (FIXME). However, if the div blocks the entire pipeline, that sounds to be pretty expensive. Let CodeGen to take care this transformation. This patch sees 6% on a benchmark. rdar://15032743 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191037 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Don't allow turning vector-of-pointer loads into vector-of-integer.Benjamin Kramer2013-09-191-0/+10
| | | | | | The code below can't handle any pointers. PR17293. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191036 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 horizontal vector reduction cost modelYi Jiang2013-09-191-0/+271
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191021 91177308-0d34-0410-b5e6-96231b3b80d8
* GVN proceeds in the presence of dead code.Shuxin Yang2013-09-198-22/+220
| | | | | | | | | | | | | | | | | | | | | | | This is how it ignores the dead code: 1) When a dead branch target, say block B, is identified, all the blocks dominated by B is dead as well. 2) The PHIs of those blocks in dominance-frontier(B) is updated such that the operands corresponding to dead predecessors are replaced by "UndefVal". Using lattice's jargon, the "UndefVal" is the "Top" in essence. Phi node like this "phi(v1 bb1, undef xx)" will be optimized into "v1" if v1 is constant, or v1 is an instruction which dominate this PHI node. 3) When analyzing the availability of a load L, all dead mem-ops which L depends on disguise as a load which evaluate exactly same value as L. 4) The dead mem-ops will be materialized as "UndefVal" during code motion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191017 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Wrap indirect functions.Evgeniy Stepanov2013-09-191-0/+21
| | | | | | | | | | Adds a flag to the MemorySanitizer pass that enables runtime rewriting of indirect calls. This is part of MSanDR implementation and is needed to return control to the DynamiRio-based helper tool on transition between instrumented and non-instrumented modules. Disabled by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191006 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGCombiner: Don't fold vector muls with constants that look like a splat of ↵Benjamin Kramer2013-09-191-0/+18
| | | | | | | | a power of 2 but differ in bit width. PR17283. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191000 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Make constant vector test case endian-independentJustin Holewinski2013-09-191-3/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190998 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Support constant vector globalsJustin Holewinski2013-09-191-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190997 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add support for the v8 cryptography extensions.Amara Emerson2013-09-197-1/+300
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190996 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: FrameIndex addressing modes do have a base register.Tim Northover2013-09-191-0/+22
| | | | | | | | | | | | | | When selecting the DAG (add (WrapperRIP ...), (FrameIndex ...)), X86 code had spotted the FrameIndex possibility and was working out whether it could fold the WrapperRIP into this. The test for forming a %rip version is notionally whether we already have a base or index register (%rip precludes both), but we were forgetting to account for the register that would be inserted later to access the frame. rdar://problem/15024520 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190995 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix two issues regarding Got pointer (GP) setup.Reed Kotler2013-09-181-10/+12
| | | | | | | | | | | | | | | | | 1) make sure that the first two instructions of the sequence cannot separate from each other. The linker requires that they be sequential. If they get separated, it can still work but it will not work in all cases because the first of the instructions mostly involves the hi part of the pc relative offset and that part changes slowly. You would have to be at the right boundary for this to matter. 2) make sure that this sequence begins on a longword boundary. There appears to be a bug in binutils which makes some of these calculations get messed up if the instruction sequence does not begin on a longword boundary. This is being investigated with the appropriate binutils folks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190966 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug info: Get rid of the VLA indirection hack in FastISel.Adrian Prantl2013-09-182-5/+7
| | | | | | | | Use the DIVariable::isIndirect() flag set by the frontend instead of guessing whether to set the machine location's indirection bit. Paired commit with CFE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190961 91177308-0d34-0410-b5e6-96231b3b80d8
* Attempt to fix llvm-ppc64-linux2 buildbot failure by addingPreston Gurd2013-09-181-1/+1
| | | | | | | | -march=x86 to SLM test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190958 91177308-0d34-0410-b5e6-96231b3b80d8
* Verify that llvm can generate the prefetchw instruction when the CPU isPreston Gurd2013-09-181-0/+2
| | | | | | | | | | Atom Silvermont. Patch by Sriram Murali. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190957 91177308-0d34-0410-b5e6-96231b3b80d8
* Name the XCore target-specific subdirectories canonically.Chandler Carruth2013-09-184-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190940 91177308-0d34-0410-b5e6-96231b3b80d8
* A couple of tests, in llvm/test/Transforms/*/xcore, are XCore-specific. They ↵NAKAMURA Takumi2013-09-182-0/+6
| | | | | | should be excluded when XCore is not built. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190938 91177308-0d34-0410-b5e6-96231b3b80d8
* Prevent LoopVectorizer and SLPVectorizer running if the target has no vector ↵Robert Lytton2013-09-183-0/+65
| | | | | | | | | | registers. XCore target: Add XCoreTargetTransformInfo This is where getNumberOfRegisters() resides, which in turn returns the number of vector registers (=0). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190936 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-add tests from r179291 which were accidentally removed by r181177.Andrea Di Biagio2013-09-181-0/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190934 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add unsigned compare-and-branch instructionsRichard Sandiford2013-09-1828-154/+2159
| | | | | | | | | | | | | | | | For some reason I never got around to adding these at the same time as the signed versions. No idea why. I'm not sure whether this SystemZII::BranchC* stuff is useful, or whether it should just be replaced with an "is normal" flag. I'll leave that for later though. There are some boundary conditions that can be tweaked, such as preferring unsigned comparisons for equality with [128, 256), and "<= 255" over "< 256", but again I'll leave those for a separate patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190930 91177308-0d34-0410-b5e6-96231b3b80d8
* 'svn add' the test cases.Joey Gouly2013-09-185-0/+92
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190929 91177308-0d34-0410-b5e6-96231b3b80d8
* Lift alignment restrictions for load/store folding on ↵Craig Topper2013-09-181-2/+0
| | | | | | VINSERTF128/VEXTRACTF128. Fixes PR17268. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190916 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a constant folding address space place I missed.Matt Arsenault2013-09-171-0/+8
| | | | | | | | If address space 0 was smaller than the address space in a constant inttoptr/ptrtoint pair, the wrong mask size would be used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190899 91177308-0d34-0410-b5e6-96231b3b80d8
* COFF: Ensure that objects produced by LLVM link with /safesehReid Kleckner2013-09-172-0/+20
| | | | | | | | | | | | | | | | | | | | Summary: We indicate that the object files are safe by emitting a @feat.00 absolute address symbol. The address is presumably interpreted as a bitfield of features that the compiler would like to enable. Bit 0 is documented in the PE COFF spec to opt in to "registered SEH", which is what /safeseh enables. LLVM's object files are safe by default because LLVM doesn't know how to produce SEH handlers. Reviewers: Bigcheese CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1691 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190898 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert the load slicing done in r190870.Quentin Colombet2013-09-171-330/+0
| | | | | | | | To avoid regressions with bitfield optimizations, this slicing should take place later, like ISel time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190891 91177308-0d34-0410-b5e6-96231b3b80d8
* COFF: Emit all MCSymbols rather than filtering out some of themReid Kleckner2013-09-171-1/+10
| | | | | | | | | | In particular, this means we emit non-external symbols defined to variables, such as aliases or absolute addresses. This is needed to implement /safeseh, and it appears there was some confusion about what symbols to emit previously. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190888 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup handling of constant function casts.Matt Arsenault2013-09-171-1/+142
| | | | | | | | | | Some of this code is no longer necessary since int<->ptr casts are no longer occur as of r187444. This also fixes handling vectors of pointers, and adds a bunch of new testcases for vectors and address spaces. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190885 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Fix problems with large code model (PR17169).Bill Schmidt2013-09-173-8/+12
| | | | | | | | | | | | | | | Large code model on PPC64 requires creating and referencing TOC entries when using the addis/ld form of addressing. This was not being done in all cases. The changes in this patch to PPCAsmPrinter::EmitInstruction() fix this. Two test cases are also modified to reflect this requirement. Fast-isel was not creating correct code for loading floating-point constants using large code model. This also requires the addis/ld form of addressing. Previously we were using the addis/lfd shortcut which is only applicable to medium code model. One test case is modified to reflect this requirement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190882 91177308-0d34-0410-b5e6-96231b3b80d8
* Costmodel: Add support for horizontal vector reductionsArnold Schwaighofer2013-09-171-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upcoming SLP vectorization improvements will want to be able to estimate costs of horizontal reductions. Add infrastructure to support this. We model reductions as a series of (shufflevector,add) tuples ultimately followed by an extractelement. For example, for an add-reduction of <4 x float> we could generate the following sequence: (v0, v1, v2, v3) \ \ / / \ \ / + + (v0+v2, v1+v3, undef, undef) \ / ((v0+v2) + (v1+v3), undef, undef) %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef> %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7 %r = extractelement <4 x float> %bin.rdx8, i32 0 This commit adds a cost model interface "getReductionCost(Opcode, Ty, Pairwise)" that will allow clients to ask for the cost of such a reduction (as backends might generate more efficient code than the cost of the individual instructions summed up). This interface is excercised by the CostModel analysis pass which looks for reduction patterns like the one above - starting at extractelements - and if it sees a matching sequence will call the cost model interface. We will also support a second form of pairwise reduction that is well supported on common architectures (haddps, vpadd, faddp). (v0, v1, v2, v3) \ / \ / (v0+v1, v2+v3, undef, undef) \ / ((v0+v1)+(v2+v3), undef, undef, undef) %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef, <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef> %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 undef, i32 undef> %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1 %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef> %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef> %bin.rdx.1 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1 %r = extractelement <4 x float> %bin.rdx.1, i32 0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190876 91177308-0d34-0410-b5e6-96231b3b80d8
* SLPVectorizer: Don't vectorize phi nodes that use invoke valuesArnold Schwaighofer2013-09-171-0/+62
| | | | | | | | | We can't insert an insertelement after an invoke. We would have to split a critical edge. So when we see a phi node that uses an invoke we just give up. radar://14990770 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190871 91177308-0d34-0410-b5e6-96231b3b80d8
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