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* Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.Evan Cheng2009-08-042-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78126 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test.Evan Cheng2009-08-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78113 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert more Neon tests to use FileCheck.Bob Wilson2009-08-043-16/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78111 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert a few Neon tests to use FileCheck.Bob Wilson2009-08-043-20/+71
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78108 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up the handling of two-address operands in RegScavenger.Jakob Stoklund Olesen2009-08-041-0/+33
| | | | | | This fixes PR4528. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78107 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable load / store multiple pass for Thumb2. It's not using ldrd / strd yet.Evan Cheng2009-08-041-0/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78104 91177308-0d34-0410-b5e6-96231b3b80d8
* Add NEON single-precision FP support for fabs and fneg.David Goodwin2009-08-042-0/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78101 91177308-0d34-0410-b5e6-96231b3b80d8
* LowerSubregsInstructionPass::LowerExtract should not extend the live range ↵Jakob Stoklund Olesen2009-08-042-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of registers. When LowerExtract eliminates an EXTRACT_SUBREG with a kill flag, it moves the kill flag to the place where the sub-register is killed. This can accidentally overlap with the use of a sibling sub-register, and we have trouble. In the test case we have this code: Live Ins: %R0 %R1 %R2 %R2L<def> = EXTRACT_SUBREG %R2<kill>, 1 %R2H<def> = LOAD16fi <fi#-1>, 0, Mem:LD(2,4) [FixedStack-1 + 0] %R1L<def> = EXTRACT_SUBREG %R1<kill>, 1 %R0L<def> = EXTRACT_SUBREG %R0<kill>, 1 %R0H<def> = ADD16 %R2H<kill>, %R2L<kill>, %AZ<imp-def>, %AN<imp-def>, %AC0<imp-def>, %V<imp-def>, %VS<imp-def> subreg: CONVERTING: %R2L<def> = EXTRACT_SUBREG %R2<kill>, 1 subreg: eliminated! subreg: killed here: %R0H<def> = ADD16 %R2H, %R2L, %R2<imp-use,kill>, %AZ<imp-def>, %AN<imp-def>, %AC0<imp-def>, %V<imp-def>, %VS<imp-def> The kill flag on %R2 is moved to the last instruction, and the live range overlaps with the definition of %R2H: *** Bad machine code: Redefining a live physical register *** - function: f - basic block: 0x18358c0 (#0) - instruction: %R2H<def> = LOAD16fi <fi#-1>, 0, Mem:LD(2,4) [FixedStack-1 + 0] Register R2H was defined but already live. The fix is to replace EXTRACT_SUBREG with IMPLICIT_DEF instead of eliminating it completely: subreg: CONVERTING: %R2L<def> = EXTRACT_SUBREG %R2<kill>, 1 subreg: replace by: %R2L<def> = IMPLICIT_DEF %R2<kill> Note that these IMPLICIT_DEF instructions survive to the asm output. It is necessary to fix the stack-color-with-reg test case because of that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78093 91177308-0d34-0410-b5e6-96231b3b80d8
* In thumb mode, r7 is used as frame register. This fixes pr4681.Evan Cheng2009-08-041-0/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78086 91177308-0d34-0410-b5e6-96231b3b80d8
* Match common pattern for FNMAC. Add NEON SP support.David Goodwin2009-08-041-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78085 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve tests.David Goodwin2009-08-042-8/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78083 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial support for single-precision FP using NEON. Added "neonfp" attribute ↵David Goodwin2009-08-049-0/+99
| | | | | | to enable. Added patterns for some binary FP operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78081 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR4528. This scavenger assertion is too strict. The two-address value isEvan Cheng2009-08-041-0/+25
| | | | | | | | | | killed by another operand. There is probably a better fix. Either 1) scavenger can look at other operands, or 2) livevariables can be smarter about kill markers. Patches welcome. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78072 91177308-0d34-0410-b5e6-96231b3b80d8
* enhance codegen to put 16-bit character strings into the Chris Lattner2009-08-041-2/+2
| | | | | | | __TEXT,__ustring section on darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78068 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support emiting for 2/4 byte mergable strings to the ".rodata.str*"Chris Lattner2009-08-041-0/+36
| | | | | | | section on ELF targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78066 91177308-0d34-0410-b5e6-96231b3b80d8
* Use separate ValueList for metadata.Devang Patel2009-08-042-0/+93
| | | | | | | This fixes PR4666. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78056 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert recent bitcode writer patches.Devang Patel2009-08-041-5/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78053 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-gcc checks the static asm variable is valid in ↵Bill Wendling2009-08-041-0/+4
| | | | | | ValidateRegisterVariable. Make this work for PPC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78051 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed now.Bill Wendling2009-08-041-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78042 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test for PR4678Rafael Espindola2009-08-041-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78040 91177308-0d34-0410-b5e6-96231b3b80d8
* XFAIL for the moment.Bill Wendling2009-08-041-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78038 91177308-0d34-0410-b5e6-96231b3b80d8
* Constants and Metadata share ValueList. This means they must be emitted ↵Devang Patel2009-08-041-0/+5
| | | | | | interleaved (using appropriate BLOCK_IDs) otherwise ValuePtrs index gets out of sync. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78033 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. ↵Evan Cheng2009-08-041-1/+19
| | | | | | This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78030 91177308-0d34-0410-b5e6-96231b3b80d8
* Add -disable-output. Thanks Bill!Dan Gohman2009-08-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78009 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new Constant::getIntegerValue helper function, and convert aDan Gohman2009-08-031-0/+84
| | | | | | | | few places in InstCombine to use it, to fix problems handling pointer types. This fixes the recent llvm-gcc bootstrap error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78005 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower CONCAT_VECTOR during legalization instead of matching it during isel.Bob Wilson2009-08-031-0/+36
| | | | | | | Add a testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77992 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Bug 4657: register scavenger asserts with subreg loweringJakob Stoklund Olesen2009-08-031-0/+29
| | | | | | | | | | | | | | | When LowerSubregsInstructionPass::LowerInsert eliminates an INSERT_SUBREG instriction because it is an identity copy, make sure that the same registers are alive before and after the elimination. When the super-register is marked <undef> this requires inserting an IMPLICIT_DEF instruction to make sure the super register is live. Fix a related bug where a kill flag on the inserted sub-register was not transferred properly. Finally, clear the undef flag in MachineInstr::addRegisterKilled. Undef implies dead and kill implies live, so they cant both be valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77989 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a coaelescer bug. If a copy val# is extended to eliminate a ↵Evan Cheng2009-08-031-0/+46
| | | | | | non-trivially coalesced copy, and the copy kills its source register. Trim the source register's live range to the last use if possible. This fixes up kill marker to make the scavenger happy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77967 91177308-0d34-0410-b5e6-96231b3b80d8
* Unbreak Win64 CC. Step one: honour register save area, fix some alignment ↵Anton Korobeynikov2009-08-032-4/+4
| | | | | | and provide a different set of call-clobberred registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77962 91177308-0d34-0410-b5e6-96231b3b80d8
* Use movd instead of movqRafael Espindola2009-08-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77956 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass target triple string in to TargetMachine constructor.Daniel Dunbar2009-08-033-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is not just a matter of passing in the target triple from the module; currently backends are making decisions based on the build and host architecture. The goal is to migrate to making these decisions based off of the triple (in conjunction with the feature string). Thus most clients pass in the target triple, or the host triple if that is empty. This has one important change in the way behavior of the JIT and llc. For the JIT, it was previously selecting the Target based on the host (naturally), but it was setting the target machine features based on the triple from the module. Now it is setting the target machine features based on the triple of the host. For LLC, -march was previously only used to select the target, the target machine features were initialized from the module's triple (which may have been empty). Now the target triple is taken from the module, or the host's triple is used if that is empty. Then the triple is adjusted to match -march. The take away is that -march for llc is now used in conjunction with the host triple to initialize the subtarget. If users want more deterministic behavior from llc, they should use -mtriple, or set the triple in the input module. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77946 91177308-0d34-0410-b5e6-96231b3b80d8
* Use movq to move 64 bits in and out of mmx registers.Rafael Espindola2009-08-032-1/+11
| | | | | | | | Fixes PR4669 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77940 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the i12 variant of load / store opcodes if offset is zero. Now we pass ↵Evan Cheng2009-08-031-0/+85
| | | | | | all of multisource as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77939 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand LDA testcases.Andreas Bolka2009-08-022-11/+62
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* Add extra SEXT pattern.Richard Osborne2009-08-021-0/+32
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* Remove unneeded intrinsics from Blackfin backend.Jakob Stoklund Olesen2009-08-021-13/+0
| | | | | | | | | | __builtin_bfin_ones does the same as ctpop, so it can be implemented in the front-end. __builtin_bfin_loadbytes loads from an unaligned pointer with the disalignexcpt instruction. It does the same as loading from a pointer with the low bits masked. It is better if the front-end creates a masked load. We can always instruction select the masked to disalignexcpt+load. We keep csync/ssync/idle. These intrinsics represent instructions that need workarounds for some silicon revisions. We may even want to convert inline assembler to intrinsics to enable the workarounds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77917 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix issue in regscavenger when scavenging a callee-saved register that has ↵Jakob Stoklund Olesen2009-08-021-3/+3
| | | | | | not been spilled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77912 91177308-0d34-0410-b5e6-96231b3b80d8
* Never add a kill flag to a constrained physical register in a two-addr ↵Jakob Stoklund Olesen2009-08-022-6/+0
| | | | | | instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77906 91177308-0d34-0410-b5e6-96231b3b80d8
* Scavenger asserts.Jakob Stoklund Olesen2009-08-021-3/+0
| | | | | | | Allow imp-def and imp-use of anything in the scavenger asserts, just like the machine code verifier. Allow redefinition of a sub-register of a live register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77904 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some basic blackfin intrinsics.Jakob Stoklund Olesen2009-08-022-0/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77903 91177308-0d34-0410-b5e6-96231b3b80d8
* Inline assembly support for Blackfin.Jakob Stoklund Olesen2009-08-021-0/+38
| | | | | | We use the same constraints as GCC, including those that are slightly insane for inline assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77899 91177308-0d34-0410-b5e6-96231b3b80d8
* Analog Devices Blackfin back-end.Jakob Stoklund Olesen2009-08-0247-0/+1238
| | | | | | | | | | | | | | Generate code for the Blackfin family of DSPs from Analog Devices: http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html We aim to be compatible with the exsisting GNU toolchain found at: http://blackfin.uclinux.org/gf/project/toolchain The back-end is experimental. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77897 91177308-0d34-0410-b5e6-96231b3b80d8
* Test both darwin and linux.Evan Cheng2009-08-021-5/+12
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* switch to filecheck formatChris Lattner2009-08-021-12/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77841 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a problem Eli noticed where we would compile the attached ptrtointChris Lattner2009-08-011-0/+8
| | | | | | | | | | | | | | | | | to: .quad X even on a 32-bit system, where X is not 64-bits. There isn't much that we can do here, so we just print: .quad ((X) & 4294967295) instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77818 91177308-0d34-0410-b5e6-96231b3b80d8
* Add nounwind to this test.Dan Gohman2009-08-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77792 91177308-0d34-0410-b5e6-96231b3b80d8
* Hack to make this test work on platforms which aren't Macs. Fixing this Eli Friedman2009-08-011-1/+1
| | | | | | | | | | | | myself because I'm getting tired of seeing the red buildbots, which have been red since 5:30PM PDT last night. Proposed supplement to developer policy: committers should make sure to be around to watch for buildbot failures after committing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77785 91177308-0d34-0410-b5e6-96231b3b80d8
* Workaround a couple of Darwin assembler bugs.Evan Cheng2009-08-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77781 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid a problem with ulimit on Solaris & friends, patch by Edward O'Callaghan!Daniel Dunbar2009-08-011-4/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77767 91177308-0d34-0410-b5e6-96231b3b80d8
* Split t2MOVCCs since some assemblers do not recognize mov shifted register ↵Evan Cheng2009-08-011-0/+35
| | | | | | alias with predicate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77764 91177308-0d34-0410-b5e6-96231b3b80d8
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