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* InstCombine: Add a few missing combines for ANDs and ORs of sign bit tests.Benjamin Kramer2011-03-291-0/+79
| | | | | | | | On x86 we now compile "if (a < 0 && b < 0)" into testl %edi, %esi js IF.THEN git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128496 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding a test for "-inf" as well.Kevin Enderby2011-03-291-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128495 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test case for MSRi.Johnny Chen2011-03-291-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128494 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Neon SINT_TO_FP and UINT_TO_FP lowering from v4i16 to v4f32. FixesCameron Zwarich2011-03-291-0/+19
| | | | | | <rdar://problem/8875309> and <rdar://problem/9057191>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128492 91177308-0d34-0410-b5e6-96231b3b80d8
* Added support symbolic floating point constants in the MC assembler for InfinityKevin Enderby2011-03-291-0/+6
| | | | | | | and Nans with the same strings as GAS supports. rdar://8673024 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128488 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a thumb test file for printf (iOS 4.3).Johnny Chen2011-03-291-0/+76
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128487 91177308-0d34-0410-b5e6-96231b3b80d8
* A8.6.188 STC, STC2Johnny Chen2011-03-291-0/+6
| | | | | | | | | The STC_OPTION and STC2_OPTION instructions should have their coprocessor option enclosed in {}. rdar://problem/9200661 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128478 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename invalid-VLDMSDB-arm.txt to be invalid-VLDMSDB_UPD-arm.txt.Johnny Chen2011-03-291-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128477 91177308-0d34-0410-b5e6-96231b3b80d8
* Add and modify some tests.Johnny Chen2011-03-292-2/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128476 91177308-0d34-0410-b5e6-96231b3b80d8
* Get rid of the non-writeback versions VLDMDB and VSTMDB, which don't ↵Owen Anderson2011-03-292-4/+2
| | | | | | actually exist. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128461 91177308-0d34-0410-b5e6-96231b3b80d8
* Do some simple copy propagation through integer loads and stores when promotingCameron Zwarich2011-03-292-1/+54
| | | | | | | vector types. This helps a lot with inlined functions when using the ARM soft float ABI. Fixes <rdar://problem/9184212>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128453 91177308-0d34-0410-b5e6-96231b3b80d8
* Reduce test case.Rafael Espindola2011-03-291-53/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128445 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimizing (zext A + zext B) * C, to (VMULL A, C) + (VMULL B, C) during ↵Evan Cheng2011-03-291-0/+29
| | | | | | | | | | | | | | | | | | | | isel lowering to fold the zero-extend's and take advantage of no-stall back to back vmul + vmla: vmull q0, d4, d6 vmlal q0, d5, d6 is faster than vaddl q0, d4, d5 vmovl q1, d6 vmul q0, q0, q1 This allows us to vmull + vmlal for: f = vmull_u8( vget_high_u8(s), c); f = vmlal_u8(f, vget_low_u8(s), c); rdar://9197392 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128444 91177308-0d34-0410-b5e6-96231b3b80d8
* In some cases, the "fail BB dominator" may be null after the BB was split (andBill Wendling2011-03-281-1/+17
| | | | | | | | becomes reachable when before it wasn't). Check to make sure that it's not null before trying to use it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128434 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Add support for disabling "temporary label" behavior. Useful for debuggingDaniel Dunbar2011-03-281-0/+33
| | | | | | on Darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128430 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add ↵Johnny Chen2011-03-281-0/+9
| | | | | | | | | some test cases. Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128417 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the transformation that moves binary operators around selects to preserveNick Lewycky2011-03-271-0/+12
| | | | | | | the subclass optional data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128388 91177308-0d34-0410-b5e6-96231b3b80d8
* Constant folding support for calls to umul.with.overflow(), basically ↵Frits van Bommel2011-03-271-8/+33
| | | | | | identical to the smul.with.overflow() code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128379 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a small missed optimization: turn X == C ? X : Y into X == C ? C : Y. ThisNick Lewycky2011-03-271-0/+13
| | | | | | | | | | | removes one use of X which helps it pass the many hasOneUse() checks. In my analysis, this turns up very often where X = A >>exact B and that can't be simplified unless X has one use (except by increasing the lifetime of A which is generally a performance loss). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128373 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo and add a test.Cameron Zwarich2011-03-261-0/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128331 91177308-0d34-0410-b5e6-96231b3b80d8
* Collect and coalesce DBG_VALUE instructions before emitting the function.Jakob Stoklund Olesen2011-03-261-1/+1
| | | | | | | | | | | Correctly terminate the range of register DBG_VALUEs when the register is clobbered or when the basic block ends. The code is now ready to deal with variables that are sometimes in a register and sometimes on the stack. We just need to teach emitDebugLoc to say 'stack slot'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128327 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed the t2PLD and friends disassembly and add two test cases.Johnny Chen2011-03-261-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128322 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the bfi handling for or (and a mask) (and b mask). We need the twoEric Christopher2011-03-261-0/+11
| | | | | | | | | | | | | | | masks to match inversely for the code as is to work. For the example given we actually want: bfi r0, r2, #1, #1 not #0, however, given the way the pattern is written it's not possible at the moment. Fixes rdar://9177502 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128320 91177308-0d34-0410-b5e6-96231b3b80d8
* PR9561: A store with a negative offset (via GEP) could erroniously say that itBill Wendling2011-03-261-0/+22
| | | | | | | | completely overlaps a previous store, thus mistakenly deleting that store. Check for this condition. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128319 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test for A8.6.246 UMULL to both arm-tests.txt amd thumb-tests.txt.Johnny Chen2011-03-252-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128306 91177308-0d34-0410-b5e6-96231b3b80d8
* Add two test cases t2SMLABT and t2SMMULR for DisassembleThumb2Mul().Johnny Chen2011-03-251-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128305 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode ↵Johnny Chen2011-03-251-0/+9
| | | | | | | | | | | GPRRegClassID. Also add some test cases. rdar://problem/9189829 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128304 91177308-0d34-0410-b5e6-96231b3b80d8
* DisassembleThumb2LdSt() did not handle t2LDRs correctly with respect to ↵Johnny Chen2011-03-251-0/+6
| | | | | | | | | RegClass. Add two test cases. rdar://problem/9182892 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128299 91177308-0d34-0410-b5e6-96231b3b80d8
* A8.6.226 TBB, TBH:Johnny Chen2011-03-251-0/+6
| | | | | | | Add two test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128295 91177308-0d34-0410-b5e6-96231b3b80d8
* Modify DisassembleThumb2LdStEx() to be more robust/correct in light of ↵Johnny Chen2011-03-251-0/+6
| | | | | | | | | recent change to t2LDREX/t2STREX instructions. Add two test cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128293 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Improve some diagnostics on uses of '.' pseudo-symbol.Daniel Dunbar2011-03-251-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128289 91177308-0d34-0410-b5e6-96231b3b80d8
* Instruction formats of SWP/SWPB were changed from LdStExFrm to MiscFrm. ↵Johnny Chen2011-03-251-0/+3
| | | | | | | | | Modify the disassembler to handle that. rdar://problem/9184053 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128285 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit less labels for debug info and stop emitting .loc directives for ↵Jakob Stoklund Olesen2011-03-253-16/+20
| | | | | | | | | | | | DBG_VALUEs. The .dot directives don't need labels, that is a leftover from when we created line number info manually. Instructions following a DBG_VALUE can share its label since the DBG_VALUE doesn't produce any code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128284 91177308-0d34-0410-b5e6-96231b3b80d8
* Also need to handle invalid imod values for CPS2p.Johnny Chen2011-03-251-0/+4
| | | | | | | rdar://problem/9186136 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128283 91177308-0d34-0410-b5e6-96231b3b80d8
* Modify the wrong logic in the assert of DisassembleThumb2LdStDual() (the ↵Johnny Chen2011-03-251-0/+3
| | | | | | | | | register classes were changed), modify the comment to be up-to-date, and add a test case for A8.6.66 LDRD (immediate) Encoding T1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128252 91177308-0d34-0410-b5e6-96231b3b80d8
* delegate the disassembly of t2ADR to the more generic t2ADDri12/t2SUBri12 ↵Johnny Chen2011-03-251-0/+3
| | | | | | instructions, and add a test case for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128249 91177308-0d34-0410-b5e6-96231b3b80d8
* The opcode names ("tLDM", "tLDM_UPD") used for conflict resolution have been ↵Johnny Chen2011-03-241-0/+6
| | | | | | | | | | stale since the change to ("tLDMIA", "tLDMIA_UPD"). Update the conflict resolution code and add test cases for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128247 91177308-0d34-0410-b5e6-96231b3b80d8
* The ARM disassembler was confused with the 16-bit tSTMIA instruction.Johnny Chen2011-03-241-0/+3
| | | | | | | | According to A8.6.189 STM/STMIA/STMEA (Encoding T1), there's only tSTMIA_UPD available. Ignore tSTMIA for the decoder emitter and add a test case for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128246 91177308-0d34-0410-b5e6-96231b3b80d8
* Move test in x86 specific area.Devang Patel2011-03-241-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128245 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle the added VBICiv*i* NEON instructions, too.Johnny Chen2011-03-241-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128243 91177308-0d34-0410-b5e6-96231b3b80d8
* Testcase for llvm-gcc commit r128230.Eric Christopher2011-03-241-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128242 91177308-0d34-0410-b5e6-96231b3b80d8
* T2 Load/Store Multiple:Johnny Chen2011-03-241-0/+3
| | | | | | | | These instructions were changed to not embed the addressing mode within the MC instructions We also need to update the corresponding assert stmt. Also add a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128240 91177308-0d34-0410-b5e6-96231b3b80d8
* Plug a leak in the arm disassembler and put the tests back.Benjamin Kramer2011-03-242-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128238 91177308-0d34-0410-b5e6-96231b3b80d8
* Add asm parsing support w/ testcases for strex/ldrex family of instructionsBruno Cardoso Lopes2011-03-242-0/+41
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove these two test files as they cause llvm-i686-linux-vg_leak build to ↵Johnny Chen2011-03-242-8/+0
| | | | | | | | | fail 'test-llvm'. These two are test cases which should result in 'invalid instruction encoding' from running llvm-mc -disassemble. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128235 91177308-0d34-0410-b5e6-96231b3b80d8
* ADR was added with the wrong encoding for inst{24-21}, and the ARM decoder ↵Johnny Chen2011-03-241-0/+3
| | | | | | | | | | was fooled. Set the encoding bits to {0,?,?,0}, not 0. Plus delegate the disassembly of ADR to the more generic ADDri/SUBri instructions, and add a test case for that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128234 91177308-0d34-0410-b5e6-96231b3b80d8
* Keep track of directory namd and fIx regression caused by Rafael's patch ↵Devang Patel2011-03-242-1/+67
| | | | | | | | | r119613. A better approach would be to move source id handling inside MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128233 91177308-0d34-0410-b5e6-96231b3b80d8
* The r118201 added support for VORR (immediate). Update ↵Johnny Chen2011-03-241-0/+3
| | | | | | | | | ARMDisassemblerCore.cpp to disassemble the VORRiv*i* instructions properly within the DisassembleN1RegModImmFrm() function. Add a test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128226 91177308-0d34-0410-b5e6-96231b3b80d8
* Add comments to the handling of opcode CPS3p to reject invalid instruction ↵Johnny Chen2011-03-242-0/+8
| | | | | | | | | encoding, a test case of invalid CPS3p encoding and one for invalid VLDMSDB due to regs out of range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128220 91177308-0d34-0410-b5e6-96231b3b80d8
* Target/X86: [PR8777][PR8778] Tweak alloca/chkstk for Windows targets.NAKAMURA Takumi2011-03-242-1/+76
| | | | | | FIXME: Some cleanups would be needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128206 91177308-0d34-0410-b5e6-96231b3b80d8
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