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* Allow TableGen DAG arguments to be just a name.Jakob Stoklund Olesen2013-03-241-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | DAG arguments can optionally be named: (dag node, node:$name) With this change, the node is also optional: (dag node, node:$name, $name) The missing node is treated as an UnsetInit, so the above is equivalent to: (dag node, node:$name, ?:$name) This syntax is useful in output patterns where we currently require the types of variables to be repeated: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr i32:$b, i32:$c)>; This is preferable: def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177843 91177308-0d34-0410-b5e6-96231b3b80d8
* Move X86-dependent test into the right subdirectory.Benjamin Kramer2013-03-231-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177821 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the type legality check from the SelectionDAGBuilder when it lowers ↵Owen Anderson2013-03-231-0/+20
| | | | | | | | | | | | @llvm.fmuladd to ISD::FMA nodes. Performing this check unilaterally prevented us from generating FMAs when the incoming IR contained illegal vector types which would eventually be legalized to underlying types that *did* support FMA. For example, an @llvm.fmuladd on an OpenCL float16 should become a sequence of float4 FMAs, not float4 fmul+fadd's. NOTE: Because we still call the target-specific profitability hook, individual targets can reinstate the old behavior, if desired, by simply performing the legality check inside their callback hook. They can also perform more sophisticated legality checks, if, for example, some illegal vector types can be productively implemented as FMAs, but not others. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177820 91177308-0d34-0410-b5e6-96231b3b80d8
* Support in AAEvaluator to print alias queries of loads/stores with TBAA tags.Manman Ren2013-03-221-0/+104
| | | | | | | | | | Add "evaluate-tbaa" to print alias queries of loads/stores. Alias queries between pointers do not include TBAA tags. Add testing case for "placement new". TBAA currently says NoAlias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177772 91177308-0d34-0410-b5e6-96231b3b80d8
* Kill every call to @clang.arc.use in the ARC contract phase.John McCall2013-03-221-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177769 91177308-0d34-0410-b5e6-96231b3b80d8
* Update test. There may be multiple catches, but those will be cleaned up.Bill Wendling2013-03-221-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177758 91177308-0d34-0410-b5e6-96231b3b80d8
* reorder the fields in DILexicalBlockFile to match the common prefix for DIScopesDavid Blaikie2013-03-221-18/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177754 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverted r176374. In some cases the lit.site.cfg file does not get generated ↵Galina Kistanova2013-03-221-0/+5
| | | | | | in tools/clang/tools/extra. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177751 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and ↵Jyotsna Verma2013-03-224-0/+1465
| | | | | | word. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177747 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor out the DIFile parameter to DILexicalBlock to refer to the raw ↵David Blaikie2013-03-226-8/+8
| | | | | | file/directory pair git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177742 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix up test/CodeGen/R600/llvm.pow.ll for r177730Michel Danzer2013-03-221-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177736 91177308-0d34-0410-b5e6-96231b3b80d8
* tsan: fix the testDmitry Vyukov2013-03-221-1/+1
| | | | | | | | Add missed file from r177717 commit that adds __tsan_vptr_read. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177719 91177308-0d34-0410-b5e6-96231b3b80d8
* tsan: handle vptr loads speciallyDmitry Vyukov2013-03-221-0/+13
| | | | | | | | | This is required to determine ctor/dtor vs virtual call races. http://llvm-reviews.chandlerc.com/D566 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177717 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix llvm::removeUnreachableBlocks to handle unreachable loops.Evgeniy Stepanov2013-03-221-0/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177713 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Improve the result bitvect type when folding (cmp pred (load ↵Arnaud A. de Grandmaison2013-03-221-0/+12
| | | | | | | | | | | | | | | (gep GV, i)) C) to a bit test. The original code used i32, and i64 if legal. This introduced unneeded casts when they aren't legal, or when the index variable i has another type. In order of preference: try to use i's type; use the smallest fitting legal type (using an added DataLayout method); default to i32. A testcase checks that this works when the index gep operand is i16. Patch by : Ahmed Bougacha <ahmed.bougacha@gmail.com> Reviewed by : Duncan git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177712 91177308-0d34-0410-b5e6-96231b3b80d8
* Reorder the DIFile field in DILexicalBlock to become a prefix common with ↵David Blaikie2013-03-2243-89/+89
| | | | | | other DIScopes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177703 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the ARM-specific variant of this test. It's already covered byChandler Carruth2013-03-222-6/+0
| | | | | | | | | | the ARM build bots, and it adds a weird case to the test suite where a test uses as inputs files in the parent directory. Talked about this with Dave on IRC and he's fine with this approach even though it isn't optimal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177700 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the invalid opcode for Mips branch instructions in the assemblerJack Carter2013-03-221-12/+12
| | | | | | | | | | | | | | | | | | For mips a branch an 18-bit signed offset (the 16-bit offset field shifted left 2 bits) is added to the address of the instruction following the branch (not the branch itself), in the branch delay slot, to form a PC-relative effective target address. Previously, the code generator did not perform the shift of the immediate branch offset which resulted in wrong instruction opcode. This patch fixes the issue. Contributor: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177687 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch that enables the Mips assembler to use symbols for offset for ↵Jack Carter2013-03-221-0/+22
| | | | | | | | | | | | | | | instructions This patch uses the generated instruction info tables to identify memory/load store instructions. After successful matching and based on the operand type and size, it generates additional instructions to the output. Contributor: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177685 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a register-class comparison bug in PPCCTRLoopsHal Finkel2013-03-211-1/+2
| | | | | | | | | Thanks to Jakob for isolating the underlying problem from the test case in r177423. The original commit had introduced asymmetric copy operations, but these turned out to be a work-around to the real problem (the use of == instead of hasSubClassEq in PPCCTRLoops). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177679 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor the filename/directory information in DISubprogram to refer ↵David Blaikie2013-03-212-3/+3
| | | | | | directly to the pair rather than the DIFile. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177677 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the DIFile in DISubprogram to the beginning to be a common prefix along ↵David Blaikie2013-03-2126-93/+93
| | | | | | with other DIScopes git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177674 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch enables the Mips .set directive to define aliasesJack Carter2013-03-211-0/+6
| | | | | | | | | | | | | | | | | | | The .set directive in the Mips the assembler can be used to set the value of a symbol to an expression. This changes the symbol's value and type to conform to the expression's. Syntax: .set symbol, expression This patch implements the parsing of the above syntax and enables the parser to use defined symbols when parsing operands. Contributor: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177667 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement builtin_{setjmp/longjmp} on PPCHal Finkel2013-03-211-0/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This implements SJLJ lowering on PPC, making the Clang functions __builtin_{setjmp/longjmp} functional on PPC platforms. The implementation strategy is similar to that on X86, with the exception that a branch-and-link variant is used to get the right jump address. Credit goes to Bill Schmidt for suggesting the use of the unconditional bcl form (instead of the regular bl instruction) to limit return-address-cache pollution. Benchmarking the speed at -O3 of: static jmp_buf env_sigill; void foo() { __builtin_longjmp(env_sigill,1); } main() { ... for (int i = 0; i < c; ++i) { if (__builtin_setjmp(env_sigill)) { goto done; } else { foo(); } done:; } ... } vs. the same code using the libc setjmp/longjmp functions on a P7 shows that this builtin implementation is ~4x faster with Altivec enabled and ~7.25x faster with Altivec disabled. This comparison is somewhat unfair because the libc version must also save/restore the VSX registers which we don't yet support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177666 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Darwin NEON FP and increase coverageRenato Golin2013-03-216-13/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177664 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused field in DISubprogramDavid Blaikie2013-03-2187-172/+170
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177661 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for spilling VRSAVE on PPCHal Finkel2013-03-211-0/+18
| | | | | | | | | | Although there is only one Altivec VRSAVE register, it is a member of a register class, and we need the ability to spill it. Because this register is normally callee-preserved and handled by special code this has never before been necessary. However, this capability will be required by a forthcoming commit adding SjLj support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177654 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct PPC FRAMEADDR lowering using a pseudo-registerHal Finkel2013-03-211-0/+47
| | | | | | | | | | | | | | | | The old code used to lower FRAMEADDR tried to replicate the logic in the real frame-lowering code that determines whether or not the frame pointer (r31) will be used. When it seemed as through the frame pointer would not be used, the stack pointer (r1) was used instead. Unfortunately, because the stack size is not yet known, this does not work. Instead, this change introduces new always-reserved pseudo-registers (FP and FP8) that are replaced during prologue insertion with the real frame-pointer register (either r1 or r31). It is important that this intrinsic always return a valid frame address because it is used by Clang to store the frame address as part of code generation for __builtin_setjmp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177653 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid NEON SP-FP unless unsafe-math or DarwinRenato Golin2013-03-218-11/+120
| | | | | | | | | | NEON is not IEEE 754 compliant, so we should avoid lowering single-precision floating point operations with NEON unless unsafe-math is turned on. The equivalent VFP instructions are IEEE 754 compliant, but in some cores they're much slower, so some archs/OSs might still request it to be on by default, such as Swift and Darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177651 91177308-0d34-0410-b5e6-96231b3b80d8
* Update some EH tests that were violating the new EH model.Bill Wendling2013-03-213-6/+16
| | | | | | | | The landingpad instruction needs to be the first non-PHI instruction in the unwind destination block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177650 91177308-0d34-0410-b5e6-96231b3b80d8
* Move library call prototype attribute inference to functionattrsMeador Inge2013-03-215-22/+41
| | | | | | | | | | | | The simplify-libcalls pass implemented a doInitialization hook to infer function prototype attributes for well-known functions. Given that the simplify-libcalls pass is going away *and* that the functionattrs pass is already in place to deduce function attributes, I am moving this logic to the functionattrs pass. This approach was discussed during patch review: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121126/157465.html. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177619 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug info: refactor the first field of DICompileUnit to be a raw ↵David Blaikie2013-03-2040-42/+42
| | | | | | | | file/directory pair This removes the DICompileUnit special case from DIScope. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177610 91177308-0d34-0410-b5e6-96231b3b80d8
* When computing the demanded bits of Load SDNodes, make sure that we are ↵Nadav Rotem2013-03-201-0/+35
| | | | | | | | | | looking at the loaded-value operand and not the ptr result (in case of pre-inc loads). rdar://13348420 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177596 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: Swap the 2nd and 3rd parameters to DICompileUnit to match the ↵David Blaikie2013-03-2041-43/+43
| | | | | | common DIScope prefix git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177595 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused field in DICompileUnitDavid Blaikie2013-03-2098-101/+101
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177590 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct cost model for vector shift on AVX2Michael Liao2013-03-201-0/+54
| | | | | | | | | | | - After moving logic recognizing vector shift with scalar amount from DAG combining into DAG lowering, we declare to customize all vector shifts even vector shift on AVX is legal. As a result, the cost model needs special tuning to identify these legal cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177586 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor file/directory path in namespace debug info to refer directly to ↵David Blaikie2013-03-201-3/+10
| | | | | | | | the pair rather than the DIFile (paired to a Clang test - excuse the buildbot skew/fallout) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177566 91177308-0d34-0410-b5e6-96231b3b80d8
* Enhance debug info namespace test to check for context/scope referenceDavid Blaikie2013-03-201-7/+16
| | | | | | | The differing file (due to the #line directive in the original source) is for future testing improvements coming soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177560 91177308-0d34-0410-b5e6-96231b3b80d8
* Make target-specific test case in r177474 only run when that target is builtDavid Blaikie2013-03-203-1/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177545 91177308-0d34-0410-b5e6-96231b3b80d8
* Reorder the DIFile parameter in DINameSpaceDavid Blaikie2013-03-201-1/+2
| | | | | | | | Moving the DIFile parameter to immediately proceed the tag so that it will be a common prefix with other DIScopes (once the DIFile is replaced with the raw file/directory pair). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177492 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test case for PR15318 fixed in r177472Hao Liu2013-03-201-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177489 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't assume the test directory is writable, use %T to find a writableNick Lewycky2013-03-202-8/+8
| | | | | | | directory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177488 91177308-0d34-0410-b5e6-96231b3b80d8
* Test DW_TAG_namespace support in the backendDavid Blaikie2013-03-201-0/+25
| | | | | | | | This is the backend portion of a Clang test case (clang/test/CodeGenCXX/debug-info-namespace.cpp) that was roughly/coarsely testing LLVM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177487 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR15296Michael Liao2013-03-201-0/+46
| | | | | | | | | - Move SRA/SRL/SHL lowering support from DAG combination to DAG lowering to support extended 256-bit integer in AVX but not AVX2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177478 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test case regression on ARM & PPC introduced r177239David Blaikie2013-03-201-4/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177474 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor the DIFile (2nd) parameter to DITypes to be an MDNode reference to ↵David Blaikie2013-03-2040-245/+245
| | | | | | | | | a raw directory/file pair This makes DIType's first non-tag parameter the same as DIFile's, allowing them to both share the common implementation of getFilename/getDirectory in DIScope. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177467 91177308-0d34-0410-b5e6-96231b3b80d8
* Propagate DAG node ordering during type legalization and instruction selectionJustin Holewinski2013-03-204-14/+77
| | | | | | | | A node's ordering is only propagated during legalization if (a) the new node does not have an ordering (is not a CSE'd node), or (b) the new node has an ordering that is higher than the node being legalized. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177465 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix pr13145 - Naming a function like a register name confuses the asm parser.Chad Rosier2013-03-191-0/+5
| | | | | | | Patch by Stepan Dyatkovskiy <stpworld@narod.ru> rdar://13457826 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177463 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the DIFile operand to DITypes from the 4th operand to the 2nd.David Blaikie2013-03-1952-377/+377
| | | | | | | | This is another step along the way to making all DIScopes have a common prefix which can be added to in a general manner to support using directives (DW_TAG_imported_module). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177462 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a comment to the CodeGen/PowerPC/asym-regclass-copy.ll testHal Finkel2013-03-191-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177434 91177308-0d34-0410-b5e6-96231b3b80d8
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