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* Modify how the formulae are rated in Loop Strength Reduce.Quentin Colombet2013-05-313-9/+64
| | | | | | | | | | | | | | | Namely, check if the target allows to fold more that one register in the addressing mode and if yes, adjust the cost accordingly. Prior to this commit, reg1 + scale * reg2 accesses were artificially preferred to reg1 + reg2 accesses. Indeed, the cost model wrongly assumed that reg1 + reg2 needs a temporary register for the computation, whereas it was correctly estimated for reg1 + scale * reg2. <rdar://problem/13973908> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183021 91177308-0d34-0410-b5e6-96231b3b80d8
* Unit test for SCEV fix r182989, PR16130.Andrew Trick2013-05-311-3/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183017 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: permit upper-case BE/LE on setend instructionTim Northover2013-05-311-0/+4
| | | | | | Patch by Amaury de la Vieuville. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183012 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: add fstmx and fldmx instructions for assemblyTim Northover2013-05-313-0/+36
| | | | | | | | | These instructions are deprecated oddities, but we still need to be able to disassemble (and reassemble) them if and when they're encountered. Patch by Amaury de la Vieuville. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183011 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify multiplications by vectors whose elements are powers of 2.Rafael Espindola2013-05-311-0/+408
| | | | | | Patch by Andrea Di Biagio. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183005 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: fix VEXT encoding corner caseTim Northover2013-05-311-0/+5
| | | | | | | | | | The disassembly of VEXT instructions was too lax in the bits checked. This fixes the case where the instruction affects Q-registers but a misaligned lane was specified (should be UNDEFINED). Patch by Amaury de la Vieuville git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183003 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Don't use LOAD and STORE REVERSED for volatile accessesRichard Sandiford2013-05-314-24/+72
| | | | | | | | | | | | | | | | | | | Unlike most -- hopefully "all other", but I'm still checking -- memory instructions we support, LOAD REVERSED and STORE REVERSED may access the memory location several times. This means that they are not suitable for volatile loads and stores. This patch is a prerequisite for better atomic load and store support. The same principle applies there: almost all memory instructions we support are inherently atomic ("block concurrent"), but LOAD REVERSED and STORE REVERSED are exceptions. Other instructions continue to allow volatile operands. I will add positive "allows volatile" tests at the same time as the "allows atomic load or store" tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183002 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Re-enable support for virtual registers in the final outputJustin Holewinski2013-05-312-35/+35
| | | | | | | | | | | | Now that 3.3 is branched, we are re-enabling virtual registers to help iron out bugs before the next release. Some of the post-RA passes do not play well with virtual registers, so we disable them for now. The needed functionality of the PrologEpilogInserter pass is copied to a new backend-specific NVPTXPrologEpilog pass. The test for this commit is not breaking the existing tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182998 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Handle mixed track-origins and keep-going settings (llvm part).Evgeniy Stepanov2013-05-311-2/+3
| | | | | | | | | | | | | | | Before this change, each module defined a weak_odr global __msan_track_origins with a value of 1 if origin tracking is enabled, 0 if disabled. If there are modules with different values, any of them may win. If 0 wins, and there is at least one module with 1, the program will most likely crash. With this change, __msan_track_origins is only emitted if origin tracking is on. Then runtime library detects if there is at least one module with origin tracking, and enables runtime support for it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182997 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: change MOV64ri64i32 into MOV32ri64Tim Northover2013-05-311-10/+10
| | | | | | | | | | The MOV64ri64i32 instruction required hacky MCInst lowering because it was allocated as setting a GR64, but the eventual instruction ("movl") only set a GR32. This converts it into a so-called "MOV32ri64" which still accepts a (appropriate) 64-bit immediate but defines a GR32. This is then converted to the full GR64 by a SUBREG_TO_REG operation, thus keeping everyone happy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182991 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Big-endian code generation for atomic instructions.Akira Hatanaka2013-05-311-160/+335
| | | | | | | Patch by Jyun-Yan You. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182984 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply with r182909 with a fix to the calculation of the new indices forNick Lewycky2013-05-311-0/+21
| | | | | | | insertelement instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182976 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r182937 and r182877.Rafael Espindola2013-05-3025-83/+13
| | | | | | | | | r182877 broke MCJIT tests on ARM and r182937 was working around another failure by r182877. This should make the ARM bots green. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182960 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use fast isel on this test.Rafael Espindola2013-05-301-1/+1
| | | | | | | | This fixes the test on ARM. Looks like it was broken by r182877. Not sure if this is a bug on fast isel on ARM, but this should help fix the ARM bots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182937 91177308-0d34-0410-b5e6-96231b3b80d8
* Force a triple so we don't get bitten by windows' different regalloc.Benjamin Kramer2013-05-301-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182935 91177308-0d34-0410-b5e6-96231b3b80d8
* Force fragile test to the atom scheduler model.Benjamin Kramer2013-05-301-2/+4
| | | | | | | The pattern the test originally checked for doesn't occur on other -mcpu settings. On atom it's still there though slightly differently scheduled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182933 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: allow registers 8-15 in testTim Northover2013-05-301-3/+3
| | | | | | | This test was failing on some hosts when an unexpected register was used for a variable. This just extends the regexp to allow the new x86-64 registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182929 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: use sub-register sequences for MOV*r0 operationsTim Northover2013-05-3013-24/+51
| | | | | | | | | | | | Instead of having a bunch of separate MOV8r0, MOV16r0, ... pseudo-instructions, it's better to use a single MOV32r0 (which will expand to "xorl %reg, %reg") and obtain other sizes with EXTRACT_SUBREG and SUBREG_TO_REG. The encoding is smaller and partial register updates can sometimes be avoided. Until recently, this sequence was a barrier to rematerialization though. That should now be fixed so it's an appropriate time to make the change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182928 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Fix case where a sext load of an i1 type may produce anJustin Holewinski2013-05-301-0/+14
| | | | | | ld.u1 instead of an ld.u8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182924 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Enable unaligned accessesRichard Sandiford2013-05-3012-5/+386
| | | | | | | | The code to distinguish between unaligned and aligned addresses was already there, so this is mostly just a switch-on-and-test process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182920 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r182909.Evgeniy Stepanov2013-05-301-12/+0
| | | | | | | PR/16177 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182919 91177308-0d34-0410-b5e6-96231b3b80d8
* Swizzle vector inputs if it helps us eliminate shuffles.Nick Lewycky2013-05-301-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182909 91177308-0d34-0410-b5e6-96231b3b80d8
* Change how we iterate over relocations on ELF.Rafael Espindola2013-05-3077-254/+320
| | | | | | | | | | | | | | | | | | | | | | | | | | For COFF and MachO, sections semantically have relocations that apply to them. That is not the case on ELF. In relocatable objects (.o), a section with relocations in ELF has offsets to another section where the relocations should be applied. In dynamic objects and executables, relocations don't have an offset, they have a virtual address. The section sh_info may or may not point to another section, but that is not actually used for resolving the relocations. This patch exposes that in the ObjectFile API. It has the following advantages: * Most (all?) clients can handle this more efficiently. They will normally walk all relocations, so doing an effort to iterate in a particular order doesn't save time. * llvm-readobj now prints relocations in the same way the native readelf does. * probably most important, relocations that don't point to any section are now visible. This is the case of relocations in the rela.dyn section. See the updated relocation-executable.test for example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182908 91177308-0d34-0410-b5e6-96231b3b80d8
* This testcase tests command line attributes which we don't yet support.Bill Wendling2013-05-301-62/+0
| | | | | | | | In fact, we're probably going to support these flags in completely different ways. So this test is no longer valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182899 91177308-0d34-0410-b5e6-96231b3b80d8
* Order CALLSEQ_START and CALLSEQ_END nodes.Andrew Trick2013-05-292-12/+23
| | | | | | | | | | | | Fixes PR16146: gdb.base__call-ar-st.exp fails after pre-RA-sched=source fixes. Patch by Xiaoyi Guo! This also fixes an unsupported dbg.value test case. Codegen was previously incorrect but the test was passing by luck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182885 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable FastISel on ARM for Linux and NaClJF Bastien2013-05-2924-12/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | FastISel was only enabled for iOS ARM and Thumb2, this patch enables it for ARM (not Thumb2) on Linux and NaCl. Thumb2 support needs a bit more work, mainly around register class restrictions. The patch punts to SelectionDAG when doing TLS relocation on non-Darwin targets. I will fix this and other FastISel-to-SelectionDAG failures in a separate patch. The patch also forces FastISel to retain frame pointers: iOS always keeps them for backtracking (so emitted code won't change because of this), but Linux was getting much worse code that was incorrect when using big frames (such as test-suite's lencod). I'll also fix this in a later patch, it will probably require a peephole so that FastISel doesn't rematerialize frame pointers back-to-back. The test changes are straightforward, similar to: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html They also add a vararg test that got dropped in that change. I ran all of test-suite on A15 hardware with --optimize-option=-O0 and all the tests pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182877 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach ReMaterialization to be more cunning about subregistersTim Northover2013-05-292-9/+9
| | | | | | | | | | | | | | | | This allows rematerialization during register coalescing to handle more cases involving operations like SUBREG_TO_REG which might need to be rematerialized using sub-register indices. For example, code like: v1(GPR64):sub_32 = MOVZ something v2(GPR64) = COPY v1(GPR64) should be convertable to: v2(GPR64):sub_32 = MOVZ something but previously we just gave up in places like this git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182872 91177308-0d34-0410-b5e6-96231b3b80d8
* LTO+Debug Info: revert r182791.Manman Ren2013-05-291-117/+0
| | | | | | | | | | | | | Since the testing case uses ref_addr, which requires version 3+ to work, we will solve the dwarf version issue first. This patch also causes failures in one of the bots. I will update the patch accordingly in my next attempt. rdar://13926659 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182867 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Two tests missing from previous commitRichard Sandiford2013-05-292-0/+218
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182847 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Immediate compare-and-branch supportRichard Sandiford2013-05-297-100/+992
| | | | | | | This patch adds support for the CIJ and CGIJ instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182846 91177308-0d34-0410-b5e6-96231b3b80d8
* Move test that depends on the X86 backend into the right subdirectory.Benjamin Kramer2013-05-291-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182834 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Add support for leaf functions in sparc backend. Venkatraman Govindaraju2013-05-291-0/+57
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182822 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips assembler: Improve set register alias handlingJack Carter2013-05-281-2/+3
| | | | | | | | | | | | | | | | | This patch solves the problem of numeric register values not being accepted: ../set_alias.s:1:11: error: expected valid expression after comma .set r4,$4 ^ The parsing of .set directive is changed and handling of symbols in code as well to enable this feature. The test example is added. Patch by Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182807 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for llvm.vectorizer metadataPaul Redmond2013-05-286-10/+86
| | | | | | | | | | | | | | | | | | | | - llvm.loop.parallel metadata has been renamed to llvm.loop to be more generic by making the root of additional loop metadata. - Loop::isAnnotatedParallel now looks for llvm.loop and associated llvm.mem.parallel_loop_access - document llvm.loop and update llvm.mem.parallel_loop_access - add support for llvm.vectorizer.width and llvm.vectorizer.unroll - document llvm.vectorizer.* metadata - add utility class LoopVectorizerHints for getting/setting loop metadata - use llvm.vectorizer.width=1 to indicate already vectorized instead of already_vectorized - update existing tests that used llvm.loop.parallel and llvm.vectorizer.already_vectorized Reviewed by: Nadav Rotem git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182802 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: use pristine object file while processing relocationsTim Northover2013-05-283-3/+3
| | | | | | | | | | | | | | Previously we would read-modify-write the target bits when processing relocations for the MCJIT. This had the problem that when relocations were processed multiple times for the same object file (as they can be), the result is not idempotent and the values became corrupted. The solution to this is to take any bits used in the destination from the pristine object file as LLVM emitted it. This should fix PR16013 and remote MCJIT on ARM ELF targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182800 91177308-0d34-0410-b5e6-96231b3b80d8
* LTO+Debug Info: correctly emit inlined_subroutine when the inlined callee isManman Ren2013-05-281-0/+117
| | | | | | | | | | | | | from a different CU. We used to print out an error message and fail to generate inlined_subroutine. If we use ref_addr in the generated DWARF, the DWARF version should be 3 or above. rdar://13926659 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182791 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend RemapInstruction and friends to take an optional new parameter, a ↵James Molloy2013-05-281-0/+15
| | | | | | | | ValueMaterializer. Extend LinkModules to pass a ValueMaterializer to RemapInstruction and friends to lazily create Functions for lazily linked globals. This is a big win when linking small modules with large (mostly unused) library modules. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182776 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Fix argument shadow alignment.Evgeniy Stepanov2013-05-281-0/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182771 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Register compare-and-branch supportRichard Sandiford2013-05-2819-49/+1105
| | | | | | | | | | | | | | | This patch adds support for the CRJ and CGRJ instructions. Support for the immediate forms will be a separate patch. The architecture has a large number of comparison instructions. I think it's generally better to concentrate on using the "best" comparison instruction first and foremost, then only use something like CRJ if CR really was the natual choice of comparison instruction. The patch therefore opportunistically converts separate CR and BRC instructions into a single CRJ while emitting instructions in ISelLowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182764 91177308-0d34-0410-b5e6-96231b3b80d8
* Make BasicAliasAnalysis recognize the fact a noalias argument cannot alias ↵Michael Kuperstein2013-05-281-0/+23
| | | | | | another argument, even if the other argument is not itself marked noalias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182755 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert sqrt functions into sqrt instructions when -ffast-math is in effect.Preston Gurd2013-05-271-0/+60
| | | | | | | | | | | | | | | | When -ffast-math is in effect (on Linux, at least), clang defines __FINITE_MATH_ONLY__ > 0 when including <math.h>. This causes the preprocessor to include <bits/math-finite.h>, which renames the sqrt functions. For instance, "sqrt" is renamed as "__sqrt_finite". This patch adds the 3 new names in such a way that they will be treated as equivalent to their respective original names. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182739 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a cpu to try to bring back the atom bots.Rafael Espindola2013-05-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182734 91177308-0d34-0410-b5e6-96231b3b80d8
* Prefer to duplicate PPC Altivec loads when expanding unaligned loadsHal Finkel2013-05-261-12/+13
| | | | | | | | | | | | | | | | | | | When expanding unaligned Altivec loads, we use the decremented offset trick to prevent page faults. Unfortunately, if we have a sequence of consecutive unaligned loads, this leads to suboptimal code generation because the 'extra' load from the first unaligned load can be combined with the base load from the second (but only if the decremented offset trick is not used for the first). Search up and down the chain, through loads and token factors, looking for consecutive loads, and if one is found, don't use the offset reduction trick. These duplicate loads are later combined to yield the desired sequence (in the future, we might want a more-powerful chain search, but that will require some changes to allow the combiner routines to access the AA object). This should complete the initial implementation of the optimized unaligned Altivec load expansion. There is some refactoring that should be done, but that will happen when the unaligned store expansion is added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182719 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR16143: Insert DEBUG_VALUE before terminator.Andrew Trick2013-05-261-0/+130
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182717 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for DWARF line number table entries for values in the instructionCameron Zwarich2013-05-251-4/+10
| | | | | | stream. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182712 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC: Combine duplicate (offset) lvsl Altivec intrinsicsHal Finkel2013-05-251-0/+6
| | | | | | | | | The lvsl permutation control instruction is a function only of the alignment of the pointer operand (relative to the 16-byte natural alignment of Altivec vectors). As a result, multiple lvsl intrinsics where the operands differ by a multiple of 16 can be combined. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182708 91177308-0d34-0410-b5e6-96231b3b80d8
* Track IR ordering of SelectionDAG nodes 4/4.Andrew Trick2013-05-253-0/+49
| | | | | | Unit test cases for -pre-RA-sched=source. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182706 91177308-0d34-0410-b5e6-96231b3b80d8
* Track IR ordering of SelectionDAG nodes 3/4.Andrew Trick2013-05-256-14/+14
| | | | | | | Remove the old IR ordering mechanism and switch to new one. Fix unit test failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182704 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC: Initial support for permutation-based unaligned Altivec loadsHal Finkel2013-05-241-0/+45
| | | | | | | | | | | | | | | | | | Altivec only directly supports aligned loads, but the loads have a strange property: If given an unaligned address, they truncate the address to the next lower aligned address, and load from there. This property, along with an extra load and some special-purpose permutation-control instructions that generate the appropriate permutations from the original unaligned address, allow efficient lowering of aligned loads. This code uses the trick explained in the Apple Velocity Engine optimization overview document to prevent the needed extra load from possibly causing a page fault if the original address happens to be aligned. As noted in the FIXMEs, there are several additional optimizations that can be performed to reduce the cost of these loads even more. These will be implemented in future commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182691 91177308-0d34-0410-b5e6-96231b3b80d8
* [objc-arc] KnownSafe does not imply that it is safe to perform code motion ↵Michael Gottesman2013-05-241-0/+200
| | | | | | | | across CFG edges since even if it is safe to remove RR pairs, we may still be able to move a retain/release into a loop. rdar://13949644 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182670 91177308-0d34-0410-b5e6-96231b3b80d8
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