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* LLVM Interpreter: fixed bug 16694Elena Demikhovsky2013-08-061-52/+137
| | | | | | | | | | | | | | fix for: Bug 16694 - ExecutionEngine/test-interp-vec-loadstore.ll failing on powerpc-darwin8 (http://llvm.org/bugs/show_bug.cgi?id=16694) The ExecutionEngine/test-interp-vec-loadstore.ll test has been failing on powerpc-darwin8 (on other platforms it passed) the reason of fail was wrong output by printf. this output is checked by FileCheck, but on little-endian powerpc the output numeric data were printed inside out and FileCheck reported fail. the printfs have been replaced by checking data inside test and numeric output has been replaced by the text output like : "int test passed, float test passed". The text output is checked by FileCheck. the dependency on data layout has been removed. done by Yuri Veselov (Intel) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187791 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor isInTailCallPosition handlingTim Northover2013-08-063-0/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change came about primarily because of two issues in the existing code. Niether of: define i64 @test1(i64 %val) { %in = trunc i64 %val to i32 tail call i32 @ret32(i32 returned %in) ret i64 %val } define i64 @test2(i64 %val) { tail call i32 @ret32(i32 returned undef) ret i32 42 } should be tail calls, and the function sameNoopInput is responsible. The main problem is that it is completely symmetric in the "tail call" and "ret" value, but in reality different things are allowed on each side. For these cases: 1. Any truncation should lead to a larger value being generated by "tail call" than needed by "ret". 2. Undef should only be allowed as a source for ret, not as a result of the call. Along the way I noticed that a mismatch between what this function treats as a valid truncation and what the backends see can lead to invalid calls as well (see x86-32 test case). This patch refactors the code so that instead of being based primarily on values which it recurses into when necessary, it starts by inspecting the type and considers each fundamental slot that the backend will see in turn. For example, given a pathological function that returned {{}, {{}, i32, {}}, i32} we would consider each "real" i32 in turn, and ask if it passes through unchanged. This is much closer to what the backend sees as a result of ComputeValueVTs. Aside from the bug fixes, this eliminates the recursion that's going on and, I believe, makes the bulk of the code significantly easier to understand. The trade-off is the nasty iterators needed to find the real types inside a returned value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187787 91177308-0d34-0410-b5e6-96231b3b80d8
* Factor FlattenCFG out from SimplifyCFGTom Stellard2013-08-066-126/+115
| | | | | | Patch by: Mei Ye git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187764 91177308-0d34-0410-b5e6-96231b3b80d8
* FileCheckize some of the testcases.Bill Wendling2013-08-0513-26/+39
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187756 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add missing test for r187749Tom Stellard2013-08-051-0/+48
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187754 91177308-0d34-0410-b5e6-96231b3b80d8
* LLVM Interpreter: This patch implements vector support for cast operations ↵Elena Demikhovsky2013-08-052-0/+178
| | | | | | | | | | | (zext, sext, uitofp, sitofp, trunc, fpext, fptosi, fptrunc, bitcast) and shift operations (shl, ashr, lshr) for integer and floating point data types. Added tests. Done by Yuri Veselov (mailto:Yuri.Veselov@intel.com). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187724 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Use BRCT and BRCTG to eliminate add-&-compare sequencesRichard Sandiford2013-08-053-1/+237
| | | | | | | | | | | | | | | | | This patch just uses a peephole test for "add; compare; branch" sequences within a single block. The IR optimizers already convert loops to decrement-and-branch-on-nonzero form in some cases, so even this simplistic test triggers many times during a clang bootstrap and projects/test-suite run. It looks like there are still cases where we need to more strongly prefer branches on nonzero though. E.g. I saw a case where a loop that started out with a check for 0 ended up with a check for -1. I'll try to look at that sometime. I ended up adding the Reference class because MachineInstr::readsRegister() doesn't check for subregisters (by design, as far as I could tell). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187723 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add definitions for BRCT and BRCTGRichard Sandiford2013-08-053-0/+92
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187721 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Use LOAD AND TEST to eliminate comparisons against zeroRichard Sandiford2013-08-051-0/+223
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187720 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add LOAD AND TEST instructionsRichard Sandiford2013-08-053-0/+246
| | | | | | | Just the definitions and MC support. The next patch uses them for codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187719 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512 set: added mask operations, lowering BUILD_VECTOR for i1 vector types.Elena Demikhovsky2013-08-051-0/+58
| | | | | | | Added intrinsics and tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187717 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the saving of S2. This is needed for some of the floating pointReed Kotler2013-08-045-16/+17
| | | | | | | | | | | helper functions. This can be optimized out later when the remaining parts of the helper function work is moved into the Mips16HardFloat pass. For now it forces us to use the 32 bit save/restore instructions instead of the 16 bit ones. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187712 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove "lto_on_osx" xfails, now that -rdynamic works on Darwin.Bob Wilson2013-08-045-8/+0
| | | | | | | Note that this will require a recent version of the linker for Darwin builds with LTO to pass these tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187711 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Turn fp selects into mask operations.Benjamin Kramer2013-08-043-48/+290
| | | | | | | | | | | | | | | | | | | | | | | double test(double a, double b, double c, double d) { return a<b ? c : d; } before: _test: ucomisd %xmm0, %xmm1 ja LBB0_2 movaps %xmm3, %xmm2 LBB0_2: movaps %xmm2, %xmm0 after: _test: cmpltsd %xmm1, %xmm0 andpd %xmm0, %xmm2 andnpd %xmm3, %xmm0 orpd %xmm2, %xmm0 Small speedup on Benchmarks/SmallPT git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187706 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512 set: added VEXTRACTPS instructionElena Demikhovsky2013-08-041-1/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187705 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: specify CPU on new test to fix atom buildbotTim Northover2013-08-041-1/+1
| | | | | | | Apparently Atoms use lea for stack adjustment, which we weren't looking for. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187704 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: correct tail return address calculationTim Northover2013-08-041-0/+19
| | | | | | | | | | | Due to the weird and wondeful usual arithmetic conversions, some calculations involving negative values were getting performed in uint32_t and then promoted to int64_t, which is really not a good idea. Patch by Katsuhiro Ueno. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187703 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up code for Mips16 large frame handling.Reed Kotler2013-08-041-12/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187701 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PPC64 64-bit GPR inline asm constraint matchingHal Finkel2013-08-031-0/+65
| | | | | | | | | | | | | | | Internally, the PowerPC backend names the 32-bit GPRs R[0-9]+, and names the 64-bit parent GPRs X[0-9]+. When matching inline assembly constraints with explicit register names, on PPC64 when an i64 MVT has been requested, we need to follow gcc's convention of using r[0-9]+ to refer to the 64-bit (parent) registers. At some point, we'll probably want to arrange things so that the generic code in TargetLowering uses the AsmName fields declared in *RegisterInfo.td in order to match these inline asm register constraints. If we do that, this change can be reverted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187693 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Expand vector truncating stores and extending loads.Akira Hatanaka2013-08-021-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187667 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARMv8] Add an assembler warning for the deprecated 'setend' instruction.Joey Gouly2013-08-021-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187666 91177308-0d34-0410-b5e6-96231b3b80d8
* SLPVectorizer: Fix PR16777. PHInodes may use multiple extracted values that ↵Nadav Rotem2013-08-021-0/+35
| | | | | | | | | | come from different blocks. Thanks Alexey Samsonov. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187663 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixes ARM LNT bot from SLP change in O3Renato Golin2013-08-021-0/+8
| | | | | | | | | | | | This patch fixes the multiple breakages on ARM test-suite after the SLP vectorizer was introduced by default on O3. The problem was an illegal vector type on ARMTTI::getCmpSelInstrCost() <3 x i1> which is not simple. The guard protects this code from breaking (cause of the problems) but doesn't fix the issue that is generating the odd vector in the first place, which also needs to be investigated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187658 91177308-0d34-0410-b5e6-96231b3b80d8
* Bugfix for making the DWARF debug strings and labels to code emitted as ↵Carlo Kok2013-08-021-0/+40
| | | | | | secrel32 instead of long opcodes (only for coff). This makes them debuggable with GDB (with fix for 64bits msvc) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187656 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix handling of CHECK-DAG combined with CHECK-NOTTim Northover2013-08-021-0/+1
| | | | | | Patch by Daniel Sanders. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187651 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r187597, "Bugfix for making the DWARF debug strings and labels to ↵NAKAMURA Takumi2013-08-021-40/+0
| | | | | | | | code emitted as secrel32 instead of long opcodes (only for coff). This makes them debuggable with GDB." It broke x86_64-win32 builder in llvm/test/DebugInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187642 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily revert "Debug Info Finder|Verifier: handle DbgLoc attached toEric Christopher2013-08-0214-36/+28
| | | | | | | | instructions." in an attempt to bring back some bots. This reverts commit r187609. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187638 91177308-0d34-0410-b5e6-96231b3b80d8
* fix for LLVM debug info on llvm-mips-linux where the label name uses % ↵Carlo Kok2013-08-011-1/+1
| | | | | | instead of L as a prefix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187623 91177308-0d34-0410-b5e6-96231b3b80d8
* Use function attributes to indicate that we don't want to realign the stack.Bill Wendling2013-08-016-28/+705
| | | | | | | | | Function attributes are the future! So just query whether we want to realign the stack directly from the function instead of through a random target options structure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187618 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some issues with Mips16 floating when certain intrinsics are present.Reed Kotler2013-08-011-0/+368
| | | | | | | | | | | | | | | | | This is actually an LLVM bug in the way it generates signatures for these when soft float is enabled. For example, floor ends up having the signature of int64(int64). The signature part is not the same as where the actual parameter types are recorded, and those ARE of course int64(int64) when soft float is enabled. (Yes, Mips16 hard float uses soft float but with different runtime rounes but then has to interoperate with Mips32 using normal floating point). This logic will eventually be moved to the Mips16HardFloat pass so it's not worth sorting out these issues in LLVM since nobody but Mips16 cares about these signatures, as far as I know, and even I won't eventually either. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187613 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM/Hexagon testcases can't compile x86 only testcase. Reverting change to ↵Carlo Kok2013-08-011-2/+2
| | | | | | testcase & fixing check for all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187610 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info Finder|Verifier: handle DbgLoc attached to instructions.Manman Ren2013-08-0114-28/+36
| | | | | | | | | | | | | | | | | | | | | | | | | Also remove checking of llvm.dbg.sp since it is not used in generating dwarf. Current state of Finder: DebugInfoFinder tries to list all debug info MDNodes used in a module. To list debug info MDNodes used by an instruction, DebugInfoFinder provides processDeclare, processValue and processLocation to handle DbgDeclareInst, DbgValueInst and DbgLoc attached to instructions. processModule will go through all DICompileUnits in llvm.dbg.cu and list debug info MDNodes used by the CUs. TODO: 1> Finder has a list of CUs, SPs, Types, Scopes and global variables. We need to add a list of variables that are used by DbgDeclareInst and DbgValueInst. 2> MDString fields should be null or isa<MDString> and MDNode fields should be null or isa<MDNode>. We currently use empty string or int 0 to represent null. 3> Go though Verify functions and make sure that they check field types. 4> Clean up existing testing cases to remove llvm.dbg.sp and make sure each testing case has a llvm.dbg.cu. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187609 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: Emit definitions for types with no members.David Blaikie2013-08-011-15/+33
| | | | | | The absence of members was a poor/incorrect proxy for "is definition". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187607 91177308-0d34-0410-b5e6-96231b3b80d8
* change the inlinefnlocalvar testcase so it uses a triple that's not coff ↵Carlo Kok2013-08-011-1/+1
| | | | | | (doesn't seem to matter for the testcase itself, what it tests isn't triple specific), as coff has a slightly different way of emitting what it checks for. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187604 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily xfail a test that breaks on OS X when building with LTO.Bob Wilson2013-08-011-0/+1
| | | | | | | | This is another case where internalize hides a symbol that is needed by a loadable module. I am currently investigating a proper fix but this patch will get our buildbot to pass in the meantime. <rdar://problem/14578094> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187601 91177308-0d34-0410-b5e6-96231b3b80d8
* Bugfix for making the DWARF debug strings and labels to code emitted as ↵Carlo Kok2013-08-011-0/+40
| | | | | | | | secrel32 instead of long opcodes (only for coff). This makes them debuggable with GDB. fixes Bug 16249 - LLVM generates broken debug info on Windows git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187597 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add 64-bit float load/store supportTom Stellard2013-08-0115-43/+161
| | | | | | | | | | | | | | | | | | * Added R600_Reg64 class * Added T#Index#.XY registers definition * Added v2i32 register reads from parameter and global space * Added f32 and i32 elements extraction from v2f32 and v2i32 * Added v2i32 -> v2f32 conversions Tom Stellard: - Mark vec2 operations as expand. The addition of a vec2 register class made them all legal. Patch by: Dmitry Cherkassov Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187582 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use 64-bit alignment for 64-bit kernel argumentsTom Stellard2013-08-011-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187581 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Custom lower i64 ZERO_EXTENDTom Stellard2013-08-011-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187580 91177308-0d34-0410-b5e6-96231b3b80d8
* EVEX and compressed displacement encoding for AVX512Elena Demikhovsky2013-08-011-0/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187576 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Reuse CC results for integer comparisons with zeroRichard Sandiford2013-08-012-0/+691
| | | | | | | | | | | This also fixes a bug in the predication of LR to LOCR: I'd forgotten that with these in-place instruction builds, the implicit operands need to be added manually. I think this was latent until now, but is tested by int-cmp-45.c. It also adds a CC valid mask to STOC, again tested by int-cmp-45.c. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187573 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Prefer comparisons with zeroRichard Sandiford2013-08-015-10/+54
| | | | | | | | Convert >= 1 to > 0, etc. Using comparison with zero isn't a win on its own, but it exposes more opportunities for CC reuse (the next patch). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187571 91177308-0d34-0410-b5e6-96231b3b80d8
* Add tests for Mips DSP instructions.Vladimir Medic2013-08-011-0/+44
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187570 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: add initial NEON supportTim Northover2013-08-0147-6/+9812
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: Fix Vararg handlingRobert Lytton2013-08-012-17/+55
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187565 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: Add byval handlingRobert Lytton2013-08-011-0/+58
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187563 91177308-0d34-0410-b5e6-96231b3b80d8
* Xcore targetRobert Lytton2013-08-011-0/+4
| | | | | | Fix emitArrayBound() calling OutStreamer.Emit*() multiple times when trying to print a single line git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187562 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some misc. issues with Mips16 fp stubs.Reed Kotler2013-08-011-48/+50
| | | | | | | | | | 1) They should never be inlined. 2) A naming inconsistency with gcc mips16 3) Stubs should not have the global attribute git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187555 91177308-0d34-0410-b5e6-96231b3b80d8
* Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction.Kevin Enderby2013-07-312-0/+6
| | | | | | | | | | | | While the .td entry is nice and all, it takes a pretty gross hack in ARMAsmParser::ParseInstruction() because of handling of other "subs" instructions to get it to match. Ran it by Jim Grosbach and he said it was about what he expected to make this work given the existing code. rdar://14214063 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187530 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "R600: Non vector only instruction can be scheduled on trans unit"Tom Stellard2013-07-3125-185/+73
| | | | | | This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187526 91177308-0d34-0410-b5e6-96231b3b80d8
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