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* Generalize test case to handle multiple indvars modes.Andrew Trick2011-09-131-3/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139578 91177308-0d34-0410-b5e6-96231b3b80d8
* Generalize this test's CHECK statements to handle different indvars modes.Andrew Trick2011-09-131-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139577 91177308-0d34-0410-b5e6-96231b3b80d8
* This test only makes sense with -enable-iv-rewrite.Andrew Trick2011-09-131-3/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139576 91177308-0d34-0410-b5e6-96231b3b80d8
* [indvars] Fix bugs in floating point IV range checks noticed by inspection.Andrew Trick2011-09-131-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139574 91177308-0d34-0410-b5e6-96231b3b80d8
* Conditionalize indvars test that relies on SCEV expansion of geps,Andrew Trick2011-09-121-4/+13
| | | | | | | which is only relevant with canonical IVs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139556 91177308-0d34-0410-b5e6-96231b3b80d8
* Change testcase commandline to be more strict and silence buildbotsBruno Cardoso Lopes2011-09-121-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139554 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR10845. SUBREG_TO_REG shouldn't be used when the input andBruno Cardoso Lopes2011-09-121-0/+14
| | | | | | destination types are equal! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139553 91177308-0d34-0410-b5e6-96231b3b80d8
* indvars test only relevant for -enable-iv-rewrite.Andrew Trick2011-09-121-1/+3
| | | | | | | Otherwise this case is now covered by no-iv-rewrite.ll. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139552 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a failing ELF Thumb test. I _think_ this is right, but it's not totally ↵Owen Anderson2011-09-121-1/+1
| | | | | | clear to me what this test is doing. Could someone on an ELF platform check? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139549 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP ↵Owen Anderson2011-09-121-0/+5
| | | | | | either. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139542 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert the wrong part of r139528, and fix testcases.Bruno Cardoso Lopes2011-09-122-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139541 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix encoding of PC-relative LDRSHW with an immediate offset.Owen Anderson2011-09-121-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139537 91177308-0d34-0410-b5e6-96231b3b80d8
* Conditionalize indvars tests that rely on SCEV expansion of geps,Andrew Trick2011-09-125-25/+26
| | | | | | | | which is relevant with canonical IVs. Anything else being checked by these tests is already covered by early CSE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139535 91177308-0d34-0410-b5e6-96231b3b80d8
* Not sure how CMPPS and CMPPD had already ever worked, I guess it didn't.Bruno Cardoso Lopes2011-09-122-0/+37
| | | | | | | | | | | | However with this fix it does now. Basically the operand order for the x86 target specific node is not the same as the instruction, but since the intrinsic need that specific order at the instruction definition, just change the order during legalization. Also, there were some wrong invertions of condition codes, such as GE => LE, GT => LT, fix that too. Fix PR10907. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139528 91177308-0d34-0410-b5e6-96231b3b80d8
* Port more encoding tests to decoding tests, and correct an improper Thumb2 ↵Owen Anderson2011-09-121-0/+509
| | | | | | pre-indexed load decoding this uncovered. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139522 91177308-0d34-0410-b5e6-96231b3b80d8
* Removing indvars tests that directly test canonical IVs and nothing else.Andrew Trick2011-09-126-137/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139518 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename -disable-iv-rewrite to -enable-iv-rewrite=false in preparation for ↵Andrew Trick2011-09-1210-10/+10
| | | | | | default change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139517 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix mistake in test runline.Eli Friedman2011-09-121-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139505 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for r139453, WidenIV::GetExtendedOperandRecurrence.Andrew Trick2011-09-121-0/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139504 91177308-0d34-0410-b5e6-96231b3b80d8
* Associate a MemOperand with LDWCP nodes introduced during ISel.Richard Osborne2011-09-121-0/+18
| | | | | | | This information is required if we want LDWCP to be hoisted out of loops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139495 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix disassembling of one of the register/register forms of ↵Craig Topper2011-09-111-0/+60
| | | | | | MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139486 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix disassembling of reverse register/register forms of ↵Craig Topper2011-09-111-0/+12
| | | | | | ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139485 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix disassembling of PAUSE instruction. Fixes PR10900. Also fixed NOP ↵Craig Topper2011-09-111-0/+3
| | | | | | disassembling to ignore OpSize and REX.W. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139484 91177308-0d34-0410-b5e6-96231b3b80d8
* Really un-XFAIL the testcase, like I said I would in r139458.Eli Friedman2011-09-101-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139459 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed an assert from:Richard Trieu2011-09-101-0/+1
| | | | | | | | | | | | | | | | assert("not implemented for target shuffle node"); to: assert(0 && "not implemented for target shuffle node"); This causes a test failure in CodeGen/X86/palignr.ll which has been marked as XFAIL for the time being. Test failure filed at PR10901. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139454 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 parsing and encoding for MOV(immediate).Jim Grosbach2011-09-101-0/+24
| | | | | | | Some aliases for MOV(register) also to keep existing T1 tests happy when run in thumbv7 mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139440 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test cases.Akira Hatanaka2011-09-0915-53/+53
| | | | | | | Generate code for Mips32r1 unless a Mips32r2 feature is tested. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139433 91177308-0d34-0410-b5e6-96231b3b80d8
* LDM writeback is not allowed if Rn is in the target register list.Owen Anderson2011-09-091-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139432 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.Owen Anderson2011-09-092-1/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb unconditional branches are allowed in IT blocks, and therefore should ↵Owen Anderson2011-09-091-1/+1
| | | | | | have a predicate operand, unlike conditional branches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the SelectionDAG verify that all the operands of BUILD_VECTOR have the ↵Eli Friedman2011-09-091-0/+23
| | | | | | same type. Teach DAGCombiner::visitINSERT_VECTOR_ELT not to make invalid BUILD_VECTORs. Fixes PR10897. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139407 91177308-0d34-0410-b5e6-96231b3b80d8
* Drop support for Mips1 and Mips2.Akira Hatanaka2011-09-098-80/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139405 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement vector-select support for avx256. Refactor the vblend ↵Nadav Rotem2011-09-091-0/+38
| | | | | | implementation to have tablegen match the instruction by the node type git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139400 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for MLA and MLS.Jim Grosbach2011-09-091-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139399 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for MCR, MCR2, MCRR, MCRR2.Jim Grosbach2011-09-091-0/+57
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139397 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up formatting a bit.Jim Grosbach2011-09-091-261/+258
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139396 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for LSL.Jim Grosbach2011-09-091-0/+38
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139395 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for LDRT.Jim Grosbach2011-09-091-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139393 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for LDRSHT.Jim Grosbach2011-09-091-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139392 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for LDRSH.Jim Grosbach2011-09-091-0/+55
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139391 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for LDRSBT.Jim Grosbach2011-09-091-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139390 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for LDRSB.Jim Grosbach2011-09-091-0/+55
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139389 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for LDRH.Jim Grosbach2011-09-091-0/+55
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139386 91177308-0d34-0410-b5e6-96231b3b80d8
* Shuffle a bit.Jim Grosbach2011-09-091-5/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139385 91177308-0d34-0410-b5e6-96231b3b80d8
* Drop support for Allegrex. Allegrex implements a variant of Mips2.Akira Hatanaka2011-09-098-16/+33
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139383 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.Jim Grosbach2011-09-091-0/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
* Add FIXME.Jim Grosbach2011-09-091-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139371 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark the eh.typeid.for intrinsic as being 'const', which it is insideDuncan Sands2011-09-091-0/+3
| | | | | | | | | any given function. As pointed out by John McCall, this is needed to have redundant eh.typeid.for tests be eliminated in the presence of cleanups. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139360 91177308-0d34-0410-b5e6-96231b3b80d8
* Add disassembler test for Intel syntax. Tests r139353.Craig Topper2011-09-091-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139356 91177308-0d34-0410-b5e6-96231b3b80d8
* Change default target architecture from Mips1 to Mips32r1 in preparation forAkira Hatanaka2011-09-094-6/+6
| | | | | | | | | | removing support for Mips1 and Mips2. This change and the ones that follow have been discussed with and approved by Bruno. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139344 91177308-0d34-0410-b5e6-96231b3b80d8
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