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* Add instruction encodings / disassembly support for l2rus instructions.Richard Osborne2013-01-201-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction encodings / disassembly support for l3r instructions.Richard Osborne2013-01-201-0/+44
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction encodings / disassembler support for 2rus instructions.Richard Osborne2013-01-201-0/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction encodings / disassembly support 3r instructions.Richard Osborne2013-01-201-0/+38
| | | | | | | | It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/X86/win_ftol2.ll: Add -cpu=generic to appease valgrind.NAKAMURA Takumi2013-01-201-1/+1
| | | | | | | On valgrind the processor is reported; Host CPU: athlon-fx git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172983 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 172708.Nadav Rotem2013-01-202-68/+0
| | | | | | | | | | | The optimization handles esoteric cases but adds a lot of complexity both to the X86 backend and to other backends. This optimization disables an important canonicalization of chains of SEXT nodes and makes SEXT and ZEXT asymmetrical. Disabling the canonicalization of consecutive SEXT nodes into a single node disables other DAG optimizations that assume that there is only one SEXT node. The AVX mask optimizations is one example. Additionally this optimization does not update the cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172968 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorizer: Implement a new heuristics for selecting the unroll factor.Nadav Rotem2013-01-201-0/+71
| | | | | | | | | We ignore the cpu frontend and focus on pipeline utilization. We do this because we don't have a good way to estimate the loop body size at the IR level. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172964 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the cpu type in the test.Nadav Rotem2013-01-201-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172963 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/Other/close-stderr.ll: Mark this as XFAIL:valgrind. We got 127 ↵NAKAMURA Takumi2013-01-201-0/+4
| | | | | | instead of 1 here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172956 91177308-0d34-0410-b5e6-96231b3b80d8
* The last of PR14471 - emission of constant floatsDavid Blaikie2013-01-201-28/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172941 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a latent bug exposed by recent static member debug info changes.David Blaikie2013-01-191-29/+30
| | | | | | | We weren't encoding boolean constants correctly due to modeling boolean as a signed type & then sign extending an i1 up to a byte & getting 255. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172926 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorizer: Emit memory checks into their own basic block.Benjamin Kramer2013-01-191-0/+4
| | | | | | | | | | | | | | This separates the check for "too few elements to run the vector loop" from the "memory overlap" check, giving a lot nicer code and allowing to skip the memory checks when we're not going to execute the vector code anyways. We still leave the decision of whether to emit the memory checks as branches or setccs, but it seems to be doing a good job. If ugly code pops up we may want to emit them as separate blocks too. Small speedup on MultiSource/Benchmarks/MallocBench/espresso. Most of this is legwork to allow multiple bypass blocks while updating PHIs, dominators and loop info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172902 91177308-0d34-0410-b5e6-96231b3b80d8
* On Sandybridge split unaligned 256bit stores into two xmm-sized stores. Nadav Rotem2013-01-198-27/+38
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172894 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some register allocation order dependencies.Jakob Stoklund Olesen2013-01-194-12/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172874 91177308-0d34-0410-b5e6-96231b3b80d8
* On Sandybridge loading unaligned 256bits using two XMM loads (vmovups and ↵Nadav Rotem2013-01-182-1/+22
| | | | | | vinsertf128) is faster than using a single vmovups instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172868 91177308-0d34-0410-b5e6-96231b3b80d8
* Split out DW_OP_addr for the split debug info DWARF5 proposal.Eric Christopher2013-01-181-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172857 91177308-0d34-0410-b5e6-96231b3b80d8
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-181-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Support for Mips register information sections. Mips ELF object files have a section that is dedicated to register use info. Some of this information such as the assumed Global Pointer value is used by the linker in relocation resolution. The register info file is .reginfo in o32 and .MIPS.options in 64 and n32 abi files. This patch contains the changes needed to create the sections, but leaves the actual register accounting for a future patch. Contributer: Jack Carter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172847 91177308-0d34-0410-b5e6-96231b3b80d8
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-181-1/+2
| | | | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. Removal of redundant code and formatting fixes. Contributers: Jack Carter/Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172842 91177308-0d34-0410-b5e6-96231b3b80d8
* [MC/Mach-O] Implement integrated assembler support for linker options.Daniel Dunbar2013-01-181-0/+35
| | | | | | - Also, fixup syntax errors in LangRef and missing newline in the MCAsmStreamer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172837 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/X86/Atomics-64.ll: Tweak for 2nd RUN not to overwrite %t. ↵NAKAMURA Takumi2013-01-181-2/+2
| | | | | | | | It sometimes causes spurious failure on lit win32. Feel free to prune or suppress each output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172823 91177308-0d34-0410-b5e6-96231b3b80d8
* [MC/Mach-O] Add support for linker options in Mach-O files.Daniel Dunbar2013-01-181-0/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172779 91177308-0d34-0410-b5e6-96231b3b80d8
* [MC/Mach-O] Add AsmParser support for .linker_option directive.Daniel Dunbar2013-01-181-0/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172778 91177308-0d34-0410-b5e6-96231b3b80d8
* Reverting r171325 & r172363. This was causing a mis-compile on the ↵Bill Wendling2013-01-171-128/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | self-hosted LTO build bots. Okay, here's how to reproduce the problem: 1) Build a Release (or Release+Asserts) version of clang in the normal way. 2) Using the clang & clang++ binaries from (1), build a Release (or Release+Asserts) version of the same sources, but this time enable LTO --- specify the `-flto' flag on the command line. 3) Run the ARC migrator tests: $ arcmt-test --args -triple x86_64-apple-darwin10 -fsyntax-only -x objective-c++ ./src/tools/clang/test/ARCMT/cxx-rewrite.mm You'll see that the output isn't correct (the whitespace is off). The mis-compile is in the function `RewriteBuffer::RemoveText' in the clang/lib/Rewrite/Core/Rewriter.cpp file. When that function and RewriteRope.cpp are compiled with LTO and the `arcmt-test' executable is regenerated, you'll see the error. When those files are not LTO'ed, then the output of the `arcmt-test' is fine. It is *really* hard to get a testcase out of this. I'll file a PR with what I have currently. --- Reverse-merging r172363 into '.': U include/llvm/Analysis/MemoryBuiltins.h U lib/Analysis/MemoryBuiltins.cpp --- Reverse-merging r171325 into '.': U test/Transforms/InstCombine/objsize.ll G include/llvm/Analysis/MemoryBuiltins.h G lib/Analysis/MemoryBuiltins.cpp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172756 91177308-0d34-0410-b5e6-96231b3b80d8
* Restore reverted test case, this time with REQUIRES: assertsBill Schmidt2013-01-171-0/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172747 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove bad test caseBill Schmidt2013-01-171-18/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172746 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch fixes PR13626 by providing i128 support in the returnBill Schmidt2013-01-171-0/+18
| | | | | | | | calling convention. 128-bit integers are now properly returned in GPR3 and GPR4 on PowerPC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172745 91177308-0d34-0410-b5e6-96231b3b80d8
* Add indexed load/store instructions for offset validation check.Jyotsna Verma2013-01-171-0/+36
| | | | | | | | This patch fixes bug 14902 - http://llvm.org/bugs/show_bug.cgi?id=14902 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172737 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch fixes the PPC calling convention to handle returns ofBill Schmidt2013-01-171-0/+55
| | | | | | | | | | | _Complex float and _Complex long double, by simply increasing the number of floating point registers available for return values. The test case verifies that the correct registers are loaded. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172733 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimization for the following SIGN_EXTEND pairs:Elena Demikhovsky2013-01-172-0/+80
| | | | | | | | | | | | v8i8 -> v8i64, v8i8 -> v8i32, v4i8 -> v4i64, v4i16 -> v4i64 for AVX and AVX2. Bug 14865. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172708 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the assembly and dissassembly of DW_FORM_sec_offset. Found this byEric Christopher2013-01-171-4/+8
| | | | | | | | | changing both the string of the dwo_name to be correct and the type of the statement list. Testcases all around. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172699 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the DW_AT_GNU_addr_base for the skeleton cu. Add support forEric Christopher2013-01-171-0/+1
| | | | | | | emitting the dwarf32 version of DW_FORM_sec_offset and correct disassembler support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172698 91177308-0d34-0410-b5e6-96231b3b80d8
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-174-0/+23
| | | | | | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172685 91177308-0d34-0410-b5e6-96231b3b80d8
* [IR] Add 'Append' and 'AppendUnique' module flag behaviors.Daniel Dunbar2013-01-163-1/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172659 91177308-0d34-0410-b5e6-96231b3b80d8
* Added test for r172599 which fixes bugzilla://14584,rdar://11744105.Michael Gottesman2013-01-161-0/+168
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172656 91177308-0d34-0410-b5e6-96231b3b80d8
* Make this test X86 only.Eric Christopher2013-01-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172652 91177308-0d34-0410-b5e6-96231b3b80d8
* Move this to X86.Eric Christopher2013-01-161-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172651 91177308-0d34-0410-b5e6-96231b3b80d8
* Add testcase missed yesterday from Paul Robinson.Eric Christopher2013-01-161-0/+172
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172646 91177308-0d34-0410-b5e6-96231b3b80d8
* [Linker] Change module flag linking to be more extensible.Daniel Dunbar2013-01-164-6/+21
| | | | | | | | | | - Instead of computing a bunch of buckets of different flag types, just do an incremental link resolving conflicts as they arise. - This also has the advantage of making the link result deterministic and not dependent on map iteration order. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172634 91177308-0d34-0410-b5e6-96231b3b80d8
* We want the dwarf AT_producer for assembly source files to match clang'sKevin Enderby2013-01-161-0/+8
| | | | | | | | | | | | | | | | AT_producer. Which includes clang's version information so we can tell which version of the compiler was used. This is the first of two steps to allow us to do that. This is the llvm-mc change to provide a method to set the AT_producer string. The second step, coming soon to a clang near you, will have the clang driver pass the value of getClangFullVersion() via an flag when invoking the integrated assembler on assembly source files. rdar://12955296 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172630 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce llvm::sys::getProcessTriple() function.Peter Collingbourne2013-01-1662-66/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | In r143502, we renamed getHostTriple() to getDefaultTargetTriple() as part of work to allow the user to supply a different default target triple at configure time. This change also affected the JIT. However, it is inappropriate to use the default target triple in the JIT in most circumstances because this will not necessarily match the current architecture used by the process, leading to illegal instruction and other such errors at run time. Introduce the getProcessTriple() function for use in the JIT and its clients, and cause the JIT to use it. On architectures with a single bitness, the host and process triples are identical. On other architectures, the host triple represents the architecture of the host CPU, while the process triple represents the architecture used by the host CPU to interpret machine code within the current process. For example, when executing 32-bit code on a 64-bit Linux machine, the host triple may be 'x86_64-unknown-linux-gnu', while the process triple may be 'i386-unknown-linux-gnu'. This fixes JIT for the 32-on-64-bit (and vice versa) build on non-Apple platforms. Differential Revision: http://llvm-reviews.chandlerc.com/D254 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172627 91177308-0d34-0410-b5e6-96231b3b80d8
* Move test that depends on the x86 target into a target-specific directory.Benjamin Kramer2013-01-161-0/+0
| | | | | | Should fix the arm buildbot (which only builds the arm target). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172611 91177308-0d34-0410-b5e6-96231b3b80d8
* ASan: wrap mapping scale and offset in a struct and make it a member of ASan ↵Alexey Samsonov2013-01-161-0/+41
| | | | | | passes. Add test for non-default mapping scale and offset. No functionality change git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172610 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove triple from this test, it makes it fail when X86 TTI is missing.Benjamin Kramer2013-01-161-4/+1
| | | | | | Without a triple opt falls back to NoTTI which comes closer to LSR's pre-TTI behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172609 91177308-0d34-0410-b5e6-96231b3b80d8
* reverting 172579Jack Carter2013-01-164-23/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172594 91177308-0d34-0410-b5e6-96231b3b80d8
* Akira,Jack Carter2013-01-164-0/+23
| | | | | | | | | | | | | | Hope you are feeling better. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172579 91177308-0d34-0410-b5e6-96231b3b80d8
* Split address information for DWARF5 split dwarf proposal. This involvesEric Christopher2013-01-151-1/+39
| | | | | | | | | | | | | | | using the DW_FORM_GNU_addr_index and a separate .debug_addr section which stays in the executable and is fully linked. Sneak in two other small changes: a) Print out the debug_str_offsets.dwo section. b) Change form we're expecting the entries in the debug_str_offsets.dwo section to take from ULEB128 to U32. Add tests for all of this in the fission-cu.ll test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172578 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach InstCombine to optimize extract of a value from a vector add operation ↵Nadav Rotem2013-01-151-0/+10
| | | | | | with a constant zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172576 91177308-0d34-0410-b5e6-96231b3b80d8
* 1. Hoist minus sign as high as possible in an attempt to revealShuxin Yang2013-01-152-33/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | some optimization opportunities (in the enclosing supper-expressions). rule 1. (-0.0 - X ) * Y => -0.0 - (X * Y) if expression "-0.0 - X" has only one reference. rule 2. (0.0 - X ) * Y => -0.0 - (X * Y) if expression "0.0 - X" has only one reference, and the instruction is marked "noSignedZero". 2. Eliminate negation (The compiler was already able to handle these opt if the 0.0s are replaced with -0.0.) rule 3: (0.0 - X) * (0.0 - Y) => X * Y rule 4: (0.0 - X) * C => X * -C if the expr is flagged "noSignedZero". 3. Rule 5: (X*Y) * X => (X*X) * Y if X!=Y and the expression is flagged with "UnsafeAlgebra". The purpose of this transformation is two-fold: a) to form a power expression (of X). b) potentially shorten the critical path: After transformation, the latency of the instruction Y is amortized by the expression of X*X, and therefore Y is in a "less critical" position compared to what it was before the transformation. 4. Remove the InstCombine code about simplifiying "X * select". The reasons are following: a) The "select" is somewhat architecture-dependent, therefore the higher level optimizers are not able to precisely predict if the simplification really yields any performance improvement or not. b) The "select" operator is bit complicate, and tends to obscure optimization opportunities. It is btter to keep it as low as possible in expr tree, and let CodeGen to tackle the optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172551 91177308-0d34-0410-b5e6-96231b3b80d8
* [IR] Add verification for module flags with the "require" behavior.Daniel Dunbar2013-01-151-2/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172549 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Temporarily remove ICmpEQ tests.Evgeniy Stepanov2013-01-151-54/+0
| | | | | | | They are failing on the bots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172540 91177308-0d34-0410-b5e6-96231b3b80d8
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