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* Temporarily revert "Change the informal convention of DBG_VALUE so that we ↵Adrian Prantl2013-04-306-119/+9
| | | | | | | | | | can express a" because it breaks some buildbots. This reverts commit 180816. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180819 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the informal convention of DBG_VALUE so that we can express aAdrian Prantl2013-04-306-9/+119
| | | | | | | | | | | | register-indirect address with an offset of 0. It used to be that a DBG_VALUE is a register-indirect value if the offset (operand 1) is nonzero. The new convention is that a DBG_VALUE is register-indirect if the first operand is a register and the second operand is an immediate. For plain registers use the combination reg, reg. rdar://problem/13658587 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180816 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Test for r179873.Akira Hatanaka2013-04-301-0/+64
| | | | | | | | Patch by Zoran Jovanovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180804 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Fold more shuffles of shuffles.Jim Grosbach2013-04-302-11/+10
| | | | | | | | | | | Always fold a shuffle-of-shuffle into a single shuffle when there's only one input vector in the first place. Continue to be more conservative when there's multiple inputs. rdar://13402653 PR15866 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180802 91177308-0d34-0410-b5e6-96231b3b80d8
* LocalStackSlotAllocation improvementsHal Finkel2013-04-302-6/+2
| | | | | | | | | | | | First, taking advantage of the fact that the virtual base registers are allocated in order of the local frame offsets, remove the quadratic register-searching behavior. Because of the ordering, we only need to check the last virtual base register created. Second, store the frame index in the FrameRef structure, and get the frame index and the local offset from this structure at the top of the loop iteration. This allows us to de-nest the loops in insertFrameReferenceRegisters (and I think makes the code cleaner). I also moved the needsFrameBaseReg check into the first loop over instructions so that we don't bother pushing FrameRefs for instructions that don't want a virtual base register anyway. Lastly, and this is the only functionality change, avoid the creation of single-use virtual base registers. These are currently not useful because, in general, they end up replacing what would be one r+r instruction with an add and a r+i instruction. Committing this removes the XFAIL in CodeGen/PowerPC/2007-09-07-LoadStoreIdxForms.ll Jim has okayed this off-list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180799 91177308-0d34-0410-b5e6-96231b3b80d8
* TBAA: remove !tbaa from testing cases if not used.Manman Ren2013-04-3069-639/+385
| | | | | | | | This will make it easier to turn on struct-path aware TBAA since the metadata format will change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180796 91177308-0d34-0410-b5e6-96231b3b80d8
* Set debug locations for branch instructions created during inlining, evenAdrian Prantl2013-04-301-0/+154
| | | | | | | | the inlined function has multiple returns. rdar://problem/12415623 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180793 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Addend computation for non external relocations on Macho.Rafael Espindola2013-04-301-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180790 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: fix loop-address.ll testVincent Lejeune2013-04-301-2/+2
| | | | | | Texture cache is now used when shader type is not specified git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180785 91177308-0d34-0410-b5e6-96231b3b80d8
* s tightens up the encoding description for ARM post-indexed ldr ↵Mihai Popa2013-04-301-1/+0
| | | | | | instructions. All instructions in this class have bit 4 cleared. It turns out that there is a test case for this, but it was marked XFAIL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180778 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix "Combine bit test + conditional or into simple math"David Majnemer2013-04-301-0/+109
| | | | | | | | | | This fixes the optimization introduced in r179748 and reverted in r179750. While the optimization was sound, it did not properly respect differences in bit-width. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180777 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite X86 codegen regression test with FileCheckMichael Liao2013-04-3016-34/+75
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180776 91177308-0d34-0410-b5e6-96231b3b80d8
* Collect the Addend for external relocs.Rafael Espindola2013-04-301-1/+0
| | | | | | | This fixes 2013-04-04-RelocAddend.ll. We don't have a testcase for non external relocs with an Addend. I will try to write one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180767 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: use native for aluVincent Lejeune2013-04-303-5/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180761 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add FetchInst bit to instruction defs to denote vertex/tex instructionsVincent Lejeune2013-04-301-2/+2
| | | | | | v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180755 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite test in FileCheck instead of grep in X86 codegenMichael Liao2013-04-301-4/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180754 91177308-0d34-0410-b5e6-96231b3b80d8
* TBAA: remove !tbaa from testing cases if not used.Manman Ren2013-04-2911-69/+32
| | | | | | | | This will make it easier to turn on struct-path aware TBAA since the metadata format will change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180745 91177308-0d34-0410-b5e6-96231b3b80d8
* Duplicate a testcase.Bill Wendling2013-04-291-0/+89
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180744 91177308-0d34-0410-b5e6-96231b3b80d8
* TBAA: remove !tbaa from testing cases if not used.Manman Ren2013-04-296-47/+24
| | | | | | | | This will make it easier to turn on struct-path aware TBAA since the metadata format will change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180743 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite some tests with FileCHeck in X86 codegenMichael Liao2013-04-2920-28/+85
| | | | | | | | | | | | | | | - Revise previous patches of the same purpose by fixing *) grep <PA> | not grep <PB> semantically is not the same as CHECK: <PA>{{^<PB>.*$}} as the former will check all occurrences of <PA> while the later only check the first match. As the result, CHECK needs putting in all place where <PA> occurs. *) grep <PA> | count <N> needs a final CHECK-NOT of the same pattern. (As 'CHECK-<N>' is proposed for discussion, converting 'grep | count <N>' where N > 1 is postponed.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180742 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve documentation.Adrian Prantl2013-04-291-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180738 91177308-0d34-0410-b5e6-96231b3b80d8
* Add getSymbolAlignment to the ObjectFile interface.Rafael Espindola2013-04-291-1/+0
| | | | | | | | | | | | | For regular object files this is only meaningful for common symbols. An object file format with direct support for atoms should be able to provide alignment information for all symbols. This replaces getCommonSymbolAlignment and fixes test-common-symbols-alignment.ll on darwin. This also includes a fix to MachOObjectFile::getSymbolFlags. It was marking undefined symbols as common (already tested by existing mcjit tests now that it is used). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180736 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use correct CF_END instruction on Northern Island GPUsTom Stellard2013-04-291-2/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180735 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix encoding of CF_END_{EG, R600} instructionsTom Stellard2013-04-291-0/+6
| | | | | | The EOP bit was not being encoded. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180734 91177308-0d34-0410-b5e6-96231b3b80d8
* SimplifyCFG: If convert single conditional storesArnold Schwaighofer2013-04-291-0/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This resurrects r179957, but adds code that makes sure we don't touch atomic/volatile stores: This transformation will transform a conditional store with a preceeding uncondtional store to the same location: a[i] = may-alias with a[i] load if (cond) a[i] = Y into an unconditional store. a[i] = X may-alias with a[i] load tmp = cond ? Y : X; a[i] = tmp We assume that on average the cost of a mispredicted branch is going to be higher than the cost of a second store to the same location, and that the secondary benefits of creating a bigger basic block for other optimizations to work on outway the potential case where the branch would be correctly predicted and the cost of the executing the second store would be noticably reflected in performance. hmmer's execution time improves by 30% on an imac12,2 on ref data sets. With this change we are on par with gcc's performance (gcc also performs this transformation). There was a 1.2 % performance improvement on a ARM swift chip. Other tests in the test-suite+external seem to be mostly uninfluenced in my experiments: This optimization was triggered on 41 tests such that the executable was different before/after the patch. Only 1 out of the 40 tests (dealII) was reproducable below 100% (by about .4%). Given that hmmer benefits so much I believe this to be a fair trade off. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180731 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable the MCJIT tests on 32 bit darwin.Rafael Espindola2013-04-291-0/+3
| | | | | | | I recently enabled them on 32 and 64 bit darwin, but it looks like 32 bit is still fairly broken. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180730 91177308-0d34-0410-b5e6-96231b3b80d8
* Propagate relocation info to resolveRelocation.Rafael Espindola2013-04-294-4/+4
| | | | | | This gets most of the MCJITs tests passing with MachO. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180716 91177308-0d34-0410-b5e6-96231b3b80d8
* [objc-arc] Apply the RV optimization to retains next to calls in ↵Michael Gottesman2013-04-293-51/+56
| | | | | | | | | | | | | | | ObjCARCContract instead of ObjCARCOpts. Turning retains into retainRV calls disrupts the data flow analysis in ObjCARCOpts. Thus we move it as late as we can by moving it into ObjCARCContract. We leave in the conversion from retainRV -> retain in ObjCARCOpt since it enables the dataflow analysis. rdar://10813093 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180698 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a XOR reassociation bug. Shuxin Yang2013-04-271-0/+27
| | | | | | | | | | | When Reassociator optimize "(x | C1)" ^ "(X & C2)", it may swap the two subexpressions, however, it forgot to swap cached constants (of C1 and C2) accordingly. rdar://13739160 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180676 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: convert MC-layer test to .s fileTim Northover2013-04-272-51/+48
| | | | | | | | The CodeGen aspects of this test are already covered by cfi-frame.ll; making it an assembly file reduces the risk of incidental changes affecting the test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180671 91177308-0d34-0410-b5e6-96231b3b80d8
* [objc-arc] Test cleanups.Michael Gottesman2013-04-279-14/+40
| | | | | | | | | Mainly adding paranoid checks for the closing brace of a function to help with FileCheck error readability. Also some other minor changes. No actual CHECK changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180668 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the target triple from the target machine rather than the moduleEric Christopher2013-04-271-1/+1
| | | | | | | | | | | | | | | | to determine whether or not we're on a darwin platform for debug code emitting. Solves the problem of a module with no triple on the command line and no triple in the module using non-gdb ok features on darwin. Fix up the member-pointers test to check the correct things for cross platform (DW_FORM_flag is a good prefix). Unfortunately no testcase because I have no ideas how to test something without a triple and without a triple in the module yet check precisely on two platforms. Ideas welcome. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180660 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the XFAIL out of the middle of a comment.Eric Christopher2013-04-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180659 91177308-0d34-0410-b5e6-96231b3b80d8
* Make all darwin ppc stubs local.Rafael Espindola2013-04-271-5/+5
| | | | | | | This fixes pr15763. Patch by David Fang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180657 91177308-0d34-0410-b5e6-96231b3b80d8
* Struct-path aware TBAA: change the format of TBAAStructType node.Manman Ren2013-04-271-11/+11
| | | | | | | | | We switch the order of offset and field type to make TBAAStructType node (name, parent node, offset) similar to scalar TBAA node (name, parent node). TypeIsImmutable is added to TBAAStructTag node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180654 91177308-0d34-0410-b5e6-96231b3b80d8
* Make CHECK lines a bit less strict so they also match code generated for win64.Benjamin Kramer2013-04-261-10/+10
| | | | | | Hopefully brings the windows buildbots back to life. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180630 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the interpreter to handle vector compares and additional vector ↵Nadav Rotem2013-04-265-0/+173
| | | | | | | | | | arithmetic operations. Patch by Yuri Veselov. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180626 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Initialize AMDGPUMachineFunction::ShaderType to ShaderType::COMPUTETom Stellard2013-04-261-1/+3
| | | | | | | | | | We need to intialize this to something and since clang does not set the shader type attribute and clang is used only for compute shaders, initializing it to COMPUTE seems like the best choice. Reviewed-by: Christian König <christian.koenig@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180620 91177308-0d34-0410-b5e6-96231b3b80d8
* cleanup testcase some moreAdrian Prantl2013-04-261-11/+11
| | | | | | rdar://problem/13056109 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180619 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Fix encoding of hint instruction for Thumb.Quentin Colombet2013-04-266-6/+37
| | | | | | | | | | | | | | | | "hint" space for Thumb actually overlaps the encoding space of the CPS instruction. In actuality, hints can be defined as CPS instructions where imod and M bits are all nil. Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe, sev) in DecodeT2CPSInstruction. This commit adds a proper diagnostic message for Imm0_4 and updates all tests. Patch by Mihail Popa <Mihail.Popa@arm.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180617 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing ':'.Rafael Espindola2013-04-261-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180616 91177308-0d34-0410-b5e6-96231b3b80d8
* Bugfix for the debug intrinsic handling in InstCombiner:Adrian Prantl2013-04-261-0/+100
| | | | | | | | | | | Since we can't guarantee that the original dbg.declare instrinsic is removed by LowerDbgDeclare(), we need to make sure that we are not inserting the same dbg.value intrinsic over and over. This removes tons of redundant DIEs when compiling optimized code. rdar://problem/13056109 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180615 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM/NEON: Pattern match vector integer abs to vabs.Benjamin Kramer2013-04-261-0/+91
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180604 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Now that we have a canonical form for vector integer abs, match it into ↵Benjamin Kramer2013-04-261-13/+130
| | | | | | pabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180600 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGCombiner: Canonicalize vector integer abs in the same way we do it for ↵Benjamin Kramer2013-04-261-0/+66
| | | | | | | | | | scalars. This already helps SSE2 x86 a lot because it lacks an efficient way to represent a vector select. The long term goal is to enable the backend to match a canonicalized pattern into a single instruction (e.g. vabs or pabs). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180597 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorizer: Calculate the number of pointers to disambiguate at runtime ↵Nadav Rotem2013-04-261-0/+84
| | | | | | based on the numbers of reads and writes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180593 91177308-0d34-0410-b5e6-96231b3b80d8
* Mips assembler: .set reorder supportJack Carter2013-04-251-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Mips have delayslots for certain instructions like jumps and branches. These are instructions that follow the branch or jump and are executed before the jump or branch is completed. Early Mips compilers could not cope with delayslots and left them up to the assembler. The assembler would fill the delayslots with the appropriate instruction, usually just a nop to allow correct runtime behavior. The default behavior for this is set with .set reorder. To tell the assembler that you don't want it to mess with the delayslot one used .set noreorder. For backwards compatibility we need to support .set reorder and have it be the default behavior in the assembler. Our support for it is to insert a NOP directly after an instruction with a delayslot when in .set reorder mode. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180584 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove SMLoc paired with CHECK-NOT patterns. Not functionality change.Michael Liao2013-04-251-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Pattern has source location by itself. After adding a trivial method to retrieve it, it's unnecessary to pair a source location for CHECK-NOT patterns. One thing revised after this is the diagnostic info is more accurate by pointing to the start of the CHECK-NOT pattern instead of the end of the CHECK-NOT pattern. E.g. diagnostic message previously looks like <stdin>:1:1: error: CHECK-NOT: string occurred! test ^ test.txt:1:16: note: CHECK-NOT: pattern specified here CHECK-NOT: test ^ is changed to <stdin>:1:1: error: CHECK-NOT: string occurred! test ^ test.txt:1:12: note: CHECK-NOT: pattern specified here CHECK-NOT: test ^ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180578 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM cost model: Integer div and rem is lowered to a function callArnold Schwaighofer2013-04-251-0/+450
| | | | | | | | Reflect this in the cost model. I observed this in MiBench/consumer-lame. radar://13354716 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180576 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch adds the X86FixupLEAs pass, which will reduce instructionPreston Gurd2013-04-254-1/+174
| | | | | | | | | | | latency for certain models of the Intel Atom family, by converting instructions into their equivalent LEA instructions, when it is both useful and possible to do so. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180573 91177308-0d34-0410-b5e6-96231b3b80d8
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