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* Add thumb2 sign / zero extend with rotate instructions.Evan Cheng2009-07-034-1/+135
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74755 91177308-0d34-0410-b5e6-96231b3b80d8
* Added indexed stores.Evan Cheng2009-07-032-0/+39
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74740 91177308-0d34-0410-b5e6-96231b3b80d8
* Sign extending pre/post indexed loads.Evan Cheng2009-07-021-1/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74736 91177308-0d34-0410-b5e6-96231b3b80d8
* do not try to analyze bitcasts from i64 to <2 x i32> in ComputedMaskedBits. ↵Chris Lattner2009-07-021-0/+15
| | | | | | | | | | While we could do this, doing so requires adjusting the demanded mask and the code isn't doing that yet. This fixes PR4495 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74699 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 pre/post indexed loads.Evan Cheng2009-07-022-0/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74696 91177308-0d34-0410-b5e6-96231b3b80d8
* @GOTPCREL is also rip-relative. Fix fast-isel to do the right thing.Chris Lattner2009-07-021-1/+1
| | | | | | | This fixes an llvm-gcc bootstrap problem I introduced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74691 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix yet-another bug I introduced into fastisel, this time handlingChris Lattner2009-07-021-0/+17
| | | | | | | constant pool references that weren't getting properly rip-relative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74689 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-mc/x86: Test case for x86 operand parsing.Daniel Dunbar2009-07-021-0/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74688 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an instcombine abort on a scalar-to-vector bitcast. This fixes PR4487.Dan Gohman2009-07-011-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74646 91177308-0d34-0410-b5e6-96231b3b80d8
* new test caseDevang Patel2009-07-011-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74633 91177308-0d34-0410-b5e6-96231b3b80d8
* Support stand alone metadata syntax.Devang Patel2009-07-011-0/+7
| | | | | | | | | !0 = constant metadata !{i32 21, i32 22} @llvm.blah = constant metadata !{i32 1000, i16 200, metadata !0} git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74630 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix codegen for references to available_externally symbols. This fixesChris Lattner2009-07-011-0/+69
| | | | | | | | PR4482. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74613 91177308-0d34-0410-b5e6-96231b3b80d8
* Insure that __block_holder_tmp is allocated on the stack when a byrefStuart Hastings2009-07-011-0/+8
| | | | | | | variable is present. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74610 91177308-0d34-0410-b5e6-96231b3b80d8
* CommuteChangesDestination() should check if to-be-commuted instruction ↵Evan Cheng2009-07-011-0/+130
| | | | | | defines any register. Also teaches the default commuteInstruction() to commute instruction without definitions (e.g. X86::test / ARM::tsp). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74602 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove special handling of implicit_def. Fix a couple more bugs in ↵Evan Cheng2009-07-011-0/+99
| | | | | | | | | liveintervalanalysis and coalescer handling of implicit_def. Note, isUndef marker must be placed even on implicit_def def operand or else the scavenger will not ignore it. This is necessary because -O0 path does not use liveintervalanalysis, it treats implicit_def just like any other def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74601 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some fast-isel problems selecting global variable addressing inChris Lattner2009-07-011-0/+24
| | | | | | | pic mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74582 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves ↵Evan Cheng2009-07-012-0/+256
| | | | | | the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74580 91177308-0d34-0410-b5e6-96231b3b80d8
* Add PIC load and store patterns for Thumb-2.David Goodwin2009-07-013-2/+51
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74577 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-mc: Symbols in a relocatable expression of the (a - b + cst) form areDaniel Dunbar2009-06-301-0/+7
| | | | | | | | allowed to be undefined when the expression is seen, we cannot enforce the same-section requirement until the entire assembly file has been seen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74565 91177308-0d34-0410-b5e6-96231b3b80d8
* Add thumb-2 store word, halfword, and byte.David Goodwin2009-06-303-0/+189
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74555 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve Thumb-2 jump table support.David Goodwin2009-06-301-0/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74549 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR4485.Rafael Espindola2009-06-302-1/+16
| | | | | | | | | Avoid unnecessary duplication of operand 0 of X86::FpSET_ST0_80. This duplication would cause one register to remain on the stack at the function return. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74534 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR4484.Rafael Espindola2009-06-301-0/+15
| | | | | | | | This was caused by me confounding FP0 and ST(0). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74523 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily restore the scavenger implicit_def checking code. MachineOperand ↵Evan Cheng2009-06-301-0/+116
| | | | | | isUndef mark is not being put on implicit_def of physical registers (created for parameter passing, etc.). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74519 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a bit IsUndef to MachineOperand. This indicates the def / use register ↵Evan Cheng2009-06-301-0/+122
| | | | | | | | | | | operand is defined by an implicit_def. That means it can def / use any register and passes (e.g. register scavenger) can feel free to ignore them. The register allocator, when it allocates a register to a virtual register defined by an implicit_def, can allocate any physical register without worrying about overlapping live ranges. It should mark all of operands of the said virtual register so later passes will do the right thing. This is not the best solution. But it should be a lot less fragile to having the scavenger try to track what is defined by implicit_def. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74518 91177308-0d34-0410-b5e6-96231b3b80d8
* A few more load instructions.Evan Cheng2009-06-303-0/+147
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74500 91177308-0d34-0410-b5e6-96231b3b80d8
* Array accesses are independent if the underlying arrays differ.Andreas Bolka2009-06-304-2/+49
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74499 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-mc: Accept relocatable expressions for .org, assignments, .byte, etc.Daniel Dunbar2009-06-301-1/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74498 91177308-0d34-0410-b5e6-96231b3b80d8
* Enhance tests to include shifted-register operand testing.David Goodwin2009-06-3014-19/+425
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74490 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-mc: Parse symbol attribute directives.Daniel Dunbar2009-06-301-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74487 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-mc: Parse .{,b,p2}align{,w,l} directives.Daniel Dunbar2009-06-291-0/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74478 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Thumb-2 support for TEQ amd TST.David Goodwin2009-06-294-0/+192
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74468 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb-2 testsDavid Goodwin2009-06-297-15/+65
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74464 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-mc: Recognize C++ style comments.Daniel Dunbar2009-06-291-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74463 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Improve expression parsing and implement evaluation of absolute expressions.Daniel Dunbar2009-06-291-0/+39
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74448 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't cache PHI exit values from exhaustive evaluations, becauseDan Gohman2009-06-291-0/+78
| | | | | | | | | an individual exhaustive evaluation reflects only the exit value implied by an individual exit, which may differ from the actual exit value of the loop if there are other exits. This fixes PR4477. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74447 91177308-0d34-0410-b5e6-96231b3b80d8
* FIX PR 4459.Rafael Espindola2009-06-291-0/+15
| | | | | | | | | Not sure I understand how the temp register gets used, but this fixes a bug and introduces no regressions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74446 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some tests of advanced TableGen list functionality.David Greene2009-06-292-0/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74445 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only ↵David Goodwin2009-06-291-0/+25
| | | | | | the Z flag (i.e. eq and ne). Make ARMcmpZ commutative. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74423 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement Thumb2 ldr.Evan Cheng2009-06-292-7/+102
| | | | | | | After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74420 91177308-0d34-0410-b5e6-96231b3b80d8
* Print pairwise dependence results, add testcases.Andreas Bolka2009-06-285-0/+113
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74402 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't try to split a loop when the controlling icmp instructionDan Gohman2009-06-271-0/+195
| | | | | | | doesn't have an IV-based operand. This fixes PR4471. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74399 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach LoopSimplify how to merge multiple loop exits into a single exit,Dan Gohman2009-06-271-0/+45
| | | | | | | | | | | | | | | | | when one of them can be converted to a trivial icmp and conditional branch. This addresses what is essentially a phase ordering problem. SimplifyCFG knows how to do this transformation, but it doesn't do so if the primary block has any instructions in it other than an icmp and a branch. In the given testcase, the block contains other instructions, however they are loop-invariant and can be hoisted. SimplifyCFG doesn't have LoopInfo though, so it can't hoist them. And, it's important that the blocks be merged before LoopRotation, as it doesn't support multiple-exit loops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74396 91177308-0d34-0410-b5e6-96231b3b80d8
* When a value is used multiple times within a single PHI, instructionsDan Gohman2009-06-271-0/+33
| | | | | | | | | inserted to replace that value must dominate all of of the basic blocks associated with the uses of the value in the PHI, not just one of them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74376 91177308-0d34-0410-b5e6-96231b3b80d8
* factor some logic out into a helper function, allow remat of loads from constantChris Lattner2009-06-271-2/+1
| | | | | | | globals. This implements remat-constant.ll even without aggressive-remat. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74373 91177308-0d34-0410-b5e6-96231b3b80d8
* Reimplement rip-relative addressing in the X86-64 backend. The newChris Lattner2009-06-272-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | implementation primarily differs from the former in that the asmprinter doesn't make a zillion decisions about whether or not something will be RIP relative or not. Instead, those decisions are made by isel lowering and propagated through to the asm printer. To achieve this, we: 1. Represent RIP relative addresses by setting the base of the X86 addr mode to X86::RIP. 2. When ISel Lowering decides that it is safe to use RIP, it lowers to X86ISD::WrapperRIP. When it is unsafe to use RIP, it lowers to X86ISD::Wrapper as before. 3. This removes isRIPRel from X86ISelAddressMode, representing it with a basereg of RIP instead. 4. The addressing mode matching logic in isel is greatly simplified. 5. The asmprinter is greatly simplified, notably the "NotRIPRel" predicate passed through various printoperand routines is gone now. 6. The various symbol printing routines in asmprinter now no longer infer when to emit (%rip), they just print the symbol. I think this is a big improvement over the previous situation. It does have two small caveats though: 1. I implemented a horrible "no-rip" modifier for the inline asm "P" constraint modifier. This is a short term hack, there is a much better, but more involved, solution. 2. I had to xfail an -aggressive-remat testcase because it isn't handling the use of RIP in the constant-pool reading instruction. This specific test is easy to fix without -aggressive-remat, which I intend to do next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74372 91177308-0d34-0410-b5e6-96231b3b80d8
* remove some unneeded eh info.Chris Lattner2009-06-273-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74371 91177308-0d34-0410-b5e6-96231b3b80d8
* testcase for PR4466Chris Lattner2009-06-271-0/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74367 91177308-0d34-0410-b5e6-96231b3b80d8
* When possible, use "mvn ra, rb" instead of "eor ra, rb, -1" because mvn has ↵David Goodwin2009-06-261-0/+11
| | | | | | a narrow version and eor(i) does not. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74355 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some testcases for some of the recent ScalarEvolution bug fixes.Dan Gohman2009-06-262-0/+419
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74353 91177308-0d34-0410-b5e6-96231b3b80d8
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