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* [AVX] Fix mask predicates for 256-bit UNPCKLPS/D and implementDavid Greene2011-03-025-0/+85
| | | | | | | | | | | missing patterns for them. Add a SIMD test subdirectory to hold tests for SIMD instruction selection correctness and quality. ' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126845 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate the unused CodeGenPrepare option to split critical edges.Cameron Zwarich2011-03-022-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126825 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend initial support for primitive types in PTX backendChe-Liang Chiou2011-03-029-254/+883
| | | | | | | | | | | | | | | | - Allow i16, i32, i64, float, and double types, using the native .u16, .u32, .u64, .f32, and .f64 PTX types. - Allow loading/storing of all primitive types. - Allow primitive types to be passed as parameters. - Allow selection of PTX Version and Shader Model as sub-target attributes. - Merge integer/floating-point test cases for load/store. - Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler. Patch by Justin Holewinski git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126824 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't re-use existing addrec expansions if they contain casts.Dan Gohman2011-03-021-0/+22
| | | | | | | This fixes PR9259. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126812 91177308-0d34-0410-b5e6-96231b3b80d8
* Catch more cases where 2-address pass should 3-addressify instructions. ↵Evan Cheng2011-03-022-6/+16
| | | | | | rdar://9002648. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126811 91177308-0d34-0410-b5e6-96231b3b80d8
* Make InstCombiner::FoldAndOfICmps create a ConstantRange that's theAnders Carlsson2011-03-011-0/+9
| | | | | | | | | | intersection of the LHS and RHS ConstantRanges and return "false" when the range is empty. This simplifies some code and catches some extra cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126744 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize "icmp pred (urem X, Y), Y" --> true/false depending on pred. There'sNick Lewycky2011-03-011-0/+16
| | | | | | | | more work to do here, "icmp ult (urem X, 10), 11" doesn't optimize away yet. Fixes example 3 from PR9343! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126741 91177308-0d34-0410-b5e6-96231b3b80d8
* Narrow right shifts need to encode their immediates differently from a normalBill Wendling2011-03-012-0/+13
| | | | | | | | | | | shift. 16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0> 32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0> 64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an obvious missing safety check to DAE::RemoveDeadArgumentsFromCallers.Eli Friedman2011-03-011-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126720 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete obsolete test.Dan Gohman2011-02-281-46/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126680 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo introduced by r126661: "Fix a typo which ..."Jakob Stoklund Olesen2011-02-281-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126666 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the arm's disassembler for blx that was building an MCInst without theKevin Enderby2011-02-281-0/+3
| | | | | | | needed two predicate operands before the imm operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126662 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo which cause dag combine crash. rdar://9059537.Evan Cheng2011-02-281-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126661 91177308-0d34-0410-b5e6-96231b3b80d8
* Windows codegen also dies on this, so restrict to the platform it wasDuncan Sands2011-02-281-1/+1
| | | | | | | actually tested on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126652 91177308-0d34-0410-b5e6-96231b3b80d8
* Make this test x86 specific because the ARM backend can't handle it.Duncan Sands2011-02-281-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126650 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach SimplifyCFG that (switch (select cond, X, Y)) is better expressed as a ↵Frits van Bommel2011-02-281-0/+138
| | | | | | | | | branch. Based on a patch by Alistair Lynn. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126647 91177308-0d34-0410-b5e6-96231b3b80d8
* srem doesn't actually have the same resulting sign as its numerator, you couldNick Lewycky2011-02-281-15/+5
| | | | | | | | also have a zero when numerator = denominator. Reverts parts of r126635 and r126637. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126644 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach InstCombine to fold "(shr exact X, Y) == 0" --> X == 0, fixing #1 fromNick Lewycky2011-02-281-0/+17
| | | | | | | PR9343. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126643 91177308-0d34-0410-b5e6-96231b3b80d8
* Add preliminary support for .f32 in the PTX backend.Che-Liang Chiou2011-02-286-0/+229
| | | | | | | | | | | | | | - Add appropriate TableGen patterns for fadd, fsub, fmul. - Add .f32 as the PTX type for the LLVM float type. - Allow parameters, return values, and global variable declarations to accept the float type. - Add appropriate test cases. Patch by Justin Holewinski git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126636 91177308-0d34-0410-b5e6-96231b3b80d8
* The sign of an srem instruction is the sign of its dividend (the firstNick Lewycky2011-02-281-0/+10
| | | | | | | | argument), regardless of the divisor. Teach instcombine about this and fix test7 in PR9343! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126635 91177308-0d34-0410-b5e6-96231b3b80d8
* Legalize support for fpextend of vector. PR9309.Duncan Sands2011-02-271-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126574 91177308-0d34-0410-b5e6-96231b3b80d8
* Target/X86: Always emit "push/pop GPRs" in prologue/epilogue and emit ↵NAKAMURA Takumi2011-02-271-1/+1
| | | | | | | | "spill/reload frames" for XMMs. It improves Win64's prologue/epilogue but it would not affect ia32 and amd64 (lack of nonvolatile XMMs). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126568 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR9324 / <rdar://problem/9052489> by handling the case where a PHI has ↵Cameron Zwarich2011-02-271-0/+20
| | | | | | no uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126567 91177308-0d34-0410-b5e6-96231b3b80d8
* Give a test file a more sensible name so that it can hold more test cases.Cameron Zwarich2011-02-271-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126566 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize ↵Benjamin Kramer2011-02-261-0/+26
| | | | | | | | | | | legalized code for large integer arithmetic. 1. Inform users of ADDEs with two 0 operands that it never sets carry 2. Fold other ADDs or ADDCs into the ADDE if possible It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126557 91177308-0d34-0410-b5e6-96231b3b80d8
* split this test into arch specific pieces, so the ARMChris Lattner2011-02-252-1/+15
| | | | | | | | test isn't run when the arm backend isn't built. This fixes PR9327 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126500 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "SimplifyCFG: GEPs with just one non-constant index are also cheap."Benjamin Kramer2011-02-251-1/+1
| | | | | | | Yes, there are other types than i8* and GEPs on them can produce an add+multiply. We don't consider that cheap enough to be speculatively executed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126481 91177308-0d34-0410-b5e6-96231b3b80d8
* Add patterns to use post-increment addressing for Neon VST1-lane instructions.Bob Wilson2011-02-251-0/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126477 91177308-0d34-0410-b5e6-96231b3b80d8
* SimplifyCFG: GEPs with just one non-constant index are also cheap.Benjamin Kramer2011-02-241-2/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126452 91177308-0d34-0410-b5e6-96231b3b80d8
* SimplifyCFG: GEPs with constant indices are cheap enough to be executed ↵Benjamin Kramer2011-02-241-0/+20
| | | | | | unconditionally. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126445 91177308-0d34-0410-b5e6-96231b3b80d8
* Restore r125595 (reverted in r126336) with modifications:Joerg Sonnenberger2011-02-243-0/+29
| | | | | | | | Introduce a variable in the AsmParserExtension whether [] is valid in an expression. If it is true, parse them like (). Enable this for ELF only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126443 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable support for vector sext and trunc:Nadav Rotem2011-02-242-0/+146
| | | | | | | | | | | | Limit the folding of any_ext and sext into the load operation to scalars. Limit the active-bits trunc optimization to scalars. Document vector trunc and vector sext in LangRef. Similar to commit 126080 (for enabling zext). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126424 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove obsolete tests.Devang Patel2011-02-242-368/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126402 91177308-0d34-0410-b5e6-96231b3b80d8
* Move arch specific tests in arch specific directories.Devang Patel2011-02-247-2/+156
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126401 91177308-0d34-0410-b5e6-96231b3b80d8
* Add XCore intrinsic for eeu instruction.Richard Osborne2011-02-241-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126384 91177308-0d34-0410-b5e6-96231b3b80d8
* test/lit.cfg: Add PATHEXT to 'substitution', to recognize tools on Windows ↵NAKAMURA Takumi2011-02-241-0/+9
| | | | | | | | hosts. Thanks to Danil Malyshev! Some tests on Windows use the "not" utility and fail with an error "program not executable". The reason for this error is that the name of the executable file sended to the "not" without the extension. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126383 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge information about the number of zero, one, and sign bits of live-outCameron Zwarich2011-02-241-0/+35
| | | | | | | registers at phis. This enables us to eliminate a lot of pointless zexts during the DAGCombine phase. This fixes <rdar://problem/8760114>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126380 91177308-0d34-0410-b5e6-96231b3b80d8
* change instcombine to not turn a call to non-varargs bitcast ofChris Lattner2011-02-242-13/+15
| | | | | | | | | | function prototype into a call to a varargs prototype. We do allow the xform if we have a definition, but otherwise we don't want to risk that we're changing the abi in a subtle way. On X86-64, for example, varargs require passing stuff in %al. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126363 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bug in X86 folding / unfolding table. Int_CMPSDrm and Int_CMPSSrm memoryEvan Cheng2011-02-241-0/+42
| | | | | | | | | operands starts at index 2, not 1. rdar://9045024 PR9305 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126359 91177308-0d34-0410-b5e6-96231b3b80d8
* Use DW_FORM_data2 for DW_AT_language and let users use ↵Devang Patel2011-02-231-1/+1
| | | | | | DW_LANG_lo_user=0x8000 to DW_LANG_hi_user=0xffff range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126339 91177308-0d34-0410-b5e6-96231b3b80d8
* Check only relevant strings in output to increase stability of the tests.Devang Patel2011-02-232-10/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126338 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove file. Previous commit deleted content, but left the file around.Jim Grosbach2011-02-231-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126337 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r125595, which is an X86-only undocumented assembly syntax extensionJim Grosbach2011-02-232-10/+0
| | | | | | | | | | | | enabled for all targets. Non-X86 targets should not have this behavior enabled by default. Joerg, if you would like to resubmit with the behavior conditionalized to be X86-ELF only, that's fine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126336 91177308-0d34-0410-b5e6-96231b3b80d8
* Put in the symbol table symbols only used in a .globl statement.Rafael Espindola2011-02-231-0/+26
| | | | | | Fixes PR9292. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126330 91177308-0d34-0410-b5e6-96231b3b80d8
* Add XCore intrinsic for clre instruction.Richard Osborne2011-02-231-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126322 91177308-0d34-0410-b5e6-96231b3b80d8
* Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enableRichard Osborne2011-02-231-0/+21
| | | | | | | | events on the thread and wait until a resource is ready to event. The vector of the resource that is ready is returned. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126320 91177308-0d34-0410-b5e6-96231b3b80d8
* Add XCore intrinsic for the setv instruction.Richard Osborne2011-02-231-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126315 91177308-0d34-0410-b5e6-96231b3b80d8
* Add XCore intrinsic for settw instruction.Richard Osborne2011-02-231-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126313 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a bug in the enhanced disassembler that causedSean Callanan2011-02-231-0/+2
| | | | | | | | | it to ignore valid uses of FS and GS as additional base registers in address computations. Added a test case for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126302 91177308-0d34-0410-b5e6-96231b3b80d8
* More fcopysign correctness and performance fix.Evan Cheng2011-02-231-9/+8
| | | | | | | | | | | | | | The previous codegen for the slow path (when values are in VFP / NEON registers) was incorrect if the source is NaN. The new codegen uses NEON vbsl instruction to copy the sign bit. e.g. vmov.i32 d1, #0x80000000 vbsl d1, d2, d0 If NEON is not available, it uses integer instructions to copy the sign bit. rdar://9034702 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126295 91177308-0d34-0410-b5e6-96231b3b80d8
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