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* In this patch, we teach X86_64TargetMachine that it has a ILP32Eli Bendersky2013-01-252-4/+43
| | | | | | | | | | | | | | | | | | | | | | | (defined by the x32 ABI) mode, in which case its pointers are 32-bits in size. This knowledge is also added to X86RegisterInfo that now returns the appropriate registers in getPointerRegClass. There are many outcomes to this change. In order to keep the patches separate and manageable, we start by focusing on some simple testable cases. The patch adds a test with passing a pointer to a function - focusing on the difference between the two data models for x86-64. Another test is added for handling of 'sret' arguments (and functionality is added in X86ISelLowering to make it work). A note on naming: the "x32 ABI" document refers to the AMD64 architecture (in LLVM it's distinguished by being is64Bits() in the x86 subtarget) with two variations: the LP64 (default) data model, and the ILP32 data model. This patch adds predicates to the subtarget which are consistent with this naming scheme. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173503 91177308-0d34-0410-b5e6-96231b3b80d8
* Add back a RUN line removed by mistake by a previous commitEli Bendersky2013-01-251-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173502 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction encodings / disassembly support for l4r instructions.Richard Osborne2013-01-251-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173501 91177308-0d34-0410-b5e6-96231b3b80d8
* Now that llvm-dwarfdump supports flags to specify which DWARF section to dump,Eli Bendersky2013-01-2541-45/+44
| | | | | | | | | use them in tests that run llvm-dwarfdump. This is in order to make tests as specific as possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173498 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve the !add TableGen test case.Hal Finkel2013-01-251-0/+3
| | | | | | Suggested by Sean Silva. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173481 91177308-0d34-0410-b5e6-96231b3b80d8
* Add command-line flags for DWARF dumping.Eli Bendersky2013-01-251-0/+13
| | | | | | | | | Flags for dumping specific DWARF sections added in lib/DebugInfo and llvm-dwarfdump. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173480 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction encodings / disassembly support for l5r instructions.Richard Osborne2013-01-251-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173479 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Implement exact shadow propagation for relational ICmp.Evgeniy Stepanov2013-01-251-3/+31
| | | | | | | | | Only for integers, pointers, and vectors of those. No floats. Instrumentation seems very heavy, and may need to be replaced with some approximation in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173452 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an addition operator to TableGenHal Finkel2013-01-251-0/+15
| | | | | | | This adds an !add(a, b) operator to tablegen; this will be used to cleanup the PPC register definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173445 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed the condition codes for the atomic64 min/umin code generation on ARM. ↵Silviu Baranga2013-01-251-2/+2
| | | | | | If the sutraction of the higher 32 bit parts gives a 0 result, we need to do the store operation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173437 91177308-0d34-0410-b5e6-96231b3b80d8
* MIsched: Improve the interface to SchedDFS analysis (subtrees).Andrew Trick2013-01-251-3/+0
| | | | | | | Allow the strategy to select SchedDFS. Allow the results of SchedDFS to affect initialization of the scheduler state. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173425 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch this code away from Value::isUsedInBasicBlock. That code eitherChandler Carruth2013-01-251-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | loops over instructions in the basic block or the use-def list of the value, neither of which are really efficient when repeatedly querying about values in the same basic block. What's more, we already know that the CondBB is small, and so we can do a much more efficient test by counting the uses in CondBB, and seeing if those account for all of the uses. Finally, we shouldn't blanket fail on any such instruction, instead we should conservatively assume that those instructions are part of the cost. Note that this actually fixes a bug in the pass because isUsedInBasicBlock has a really terrible bug in it. I'll fix that in my next commit, but the fix for it would make this code suddenly take the compile time hit I thought it already was taking, so I wanted to go ahead and migrate this code to a faster & better pattern. The bug in isUsedInBasicBlock was also causing other tests to test the wrong thing entirely: for example we weren't actually disabling speculation for floating point operations as intended (and tested), but the test passed because we failed to speculate them due to the isUsedInBasicBlock failure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173417 91177308-0d34-0410-b5e6-96231b3b80d8
* MISched: Add SchedDFSResult to ScheduleDAGMI to formalize theAndrew Trick2013-01-251-0/+3
| | | | | | interface and allow other strategies to select it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173413 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch implements parsing the .wordJack Carter2013-01-251-1/+4
| | | | | | | | | | directive for the Mips assembler. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173407 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Set flag neverHasSideEffects flag on some of the floating point ↵Akira Hatanaka2013-01-251-0/+13
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173401 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply chandlerc's r173342 now that the miscompile it was triggering is fixed.Benjamin Kramer2013-01-241-0/+29
| | | | | | | | | | | | | | | | | | | | | Original commit message: Plug TTI into the speculation logic, giving it a real cost interface that can be specialized by targets. The goal here is not to be more aggressive, but to just be more accurate with very obvious cases. There are instructions which are known to be truly free and which were not being modeled as such in this code -- see the regression test which is distilled from an inner loop of zlib. Everywhere the TTI cost model is insufficiently conservative I've added explicit checks with FIXME comments to go add proper modelling of these cost factors. If this causes regressions, the likely solution is to make TTI even more conservative in its cost estimates, but test cases will help here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173357 91177308-0d34-0410-b5e6-96231b3b80d8
* ConstantFolding: Add a missing folding that leads to a miscompile.Benjamin Kramer2013-01-242-1/+37
| | | | | | | | | | We use constant folding to see if an intrinsic evaluates to the same value as a constant that we know. If we don't take the undefinedness into account we get a value that doesn't match the actual implementation, and miscompiled code. This was uncovered by Chandler's simplifycfg changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173356 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r173342 temporarily. It appears to cause a very late miscompileChandler Carruth2013-01-241-29/+0
| | | | | | of stage2 in a bootstrap. Still investigating.... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173343 91177308-0d34-0410-b5e6-96231b3b80d8
* Plug TTI into the speculation logic, giving it a real cost interfaceChandler Carruth2013-01-241-0/+29
| | | | | | | | | | | | | | | | | | that can be specialized by targets. The goal here is not to be more aggressive, but to just be more accurate with very obvious cases. There are instructions which are known to be truly free and which were not being modeled as such in this code -- see the regression test which is distilled from an inner loop of zlib. Everywhere the TTI cost model is insufficiently conservative I've added explicit checks with FIXME comments to go add proper modelling of these cost factors. If this causes regressions, the likely solution is to make TTI even more conservative in its cost estimates, but test cases will help here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173342 91177308-0d34-0410-b5e6-96231b3b80d8
* Address a large chunk of this FIXME by accumulating the cost forChandler Carruth2013-01-241-0/+42
| | | | | | | unfolded constant expressions rather than checking each one independently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173341 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch the constant expression speculation cost evaluation away fromChandler Carruth2013-01-241-0/+22
| | | | | | | | | | | | | | | | | | | | a cost fuction that seems both a bit ad-hoc and also poorly suited to evaluating constant expressions. Notably, it is missing any support for trivial expressions such as 'inttoptr'. I could fix this routine, but it isn't clear to me all of the constraints its other users are operating under. The core protection that seems relevant here is avoiding the formation of a select instruction wich a further chain of select operations in a constant expression operand. Just explicitly encode that constraint. Also, update the comments and organization here to make it clear where this needs to go -- this should be driven off of real cost measurements which take into account the number of constants expressions and the depth of the constant expression tree. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173340 91177308-0d34-0410-b5e6-96231b3b80d8
* [asan] adaptive redzones for globals (the larger the global the larger is ↵Kostya Serebryany2013-01-241-0/+57
| | | | | | the redzone) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173335 91177308-0d34-0410-b5e6-96231b3b80d8
* The next phase of Mips16 hard float implementation.Reed Kotler2013-01-241-0/+256
| | | | | | | | | | | | | | | | | | Allow Mips16 routines to call Mips32 routines that have abi requirements that either arguments or return values are passed in floating point registers. This handles only the pic case. We have not done non pic for Mips16 yet in any form. The libm functions are Mips32, so with this addition we have a complete Mips16 hard float implementation. We still are not able to complete mix Mip16 and Mips32 with hard float. That will be the next phase which will have several steps. For Mips32 to freely call Mips16 some stub functions must be created. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173320 91177308-0d34-0410-b5e6-96231b3b80d8
* ConstantFolding: Evaluate GEP indices in the index type.Benjamin Kramer2013-01-231-3/+22
| | | | | | | This fixes some edge cases that we would get wrong with uint64_ts. PR14986. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173289 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction encodings / disassembly support for l6r instructions.Richard Osborne2013-01-231-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "InstCombine: Clean up weird code that talks about a modulus that's ↵Benjamin Kramer2013-01-231-0/+16
| | | | | | | | | long gone." This causes crashes during the build of compiler-rt during selfhost. Add a testcase for coverage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173279 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the heuristic to differentiate SSPStrong from SSPRequired.Bill Wendling2013-01-231-12/+2518
| | | | | | | | | | | | | | | | | | | The requirements of the strong heuristic are: * A Protector is required for functions which contain an array, regardless of type or length. * A Protector is required for functions which contain a structure/union which contains an array, regardless of type or length. Note, there is no limit to the depth of nesting. * A protector is required when the address of a local variable (i.e., stack based variable) is exposed. (E.g., such as through a local whose address is taken as part of the RHS of an assignment or a local whose address is taken as part of a function argument.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173231 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the IR attribute 'sspstrong'.Bill Wendling2013-01-232-21/+783
| | | | | | | | | | | | | | | | | | | | | | SSPStrong applies a heuristic to insert stack protectors in these situations: * A Protector is required for functions which contain an array, regardless of type or length. * A Protector is required for functions which contain a structure/union which contains an array, regardless of type or length. Note, there is no limit to the depth of nesting. * A protector is required when the address of a local variable (i.e., stack based variable) is exposed. (E.g., such as through a local whose address is taken as part of the RHS of an assignment or a local whose address is taken as part of a function argument.) This patch implements the SSPString attribute to be equivalent to SSPRequired. This will change in a subsequent patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173230 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for reverse pointer induction variables. These are loops that ↵Nadav Rotem2013-01-233-0/+195
| | | | | | | | | | | | | | | contain pointers that count backwards. For example, this is the hot loop in BZIP: do { m = *--p; *p = ( ... ); } while (--n); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173219 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction encodings / disassembly support for u10 / lu10 instructions.Richard Osborne2013-01-221-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173204 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an issue of pseudo atomic instruction DAG scheduleMichael Liao2013-01-221-0/+110
| | | | | | | | | | | | - Add list of physical registers clobbered in pseudo atomic insts Physical registers are clobbered when pseudo atomic instructions are expanded. Add them in clobber list to prevent DAG scheduler to mis-schedule them after these insns are declared side-effect free. - Add test case from Michael Kuperstein <michael.m.kuperstein@intel.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173200 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a warning when there is a macro defintion that has named parameters butKevin Enderby2013-01-221-0/+14
| | | | | | | | | | | | | | the body does not use them and it appears the body has positional parameters. This can cause unexpected results as in the added test case. As the darwin version of gas(1) which only supported positional parameters, happened to ignore the named parameters. Now that we want to support both styles of macros we issue a warning in this specific case. rdar://12861644 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173199 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Implement MipsRegisterInfo::getRegPressureLimit.Akira Hatanaka2013-01-223-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173197 91177308-0d34-0410-b5e6-96231b3b80d8
* Have the integrated assembler give an error if $1 is used as an identifier inKevin Enderby2013-01-221-0/+5
| | | | | | | | | | an expression. Currently this bug causes the line to be ignored in a release build and an assert in a debug build. rdar://13062484 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173195 91177308-0d34-0410-b5e6-96231b3b80d8
* Add forgotten test case for the x32 commitEli Bendersky2013-01-221-0/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173181 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Make sure we account for the FMA4 register immediate value, otherwise ↵Benjamin Kramer2013-01-221-0/+61
| | | | | | | | rip-rel relocations will be off by one byte. PR15040. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173176 91177308-0d34-0410-b5e6-96231b3b80d8
* Tests: rewrite 'opt ... %s' to 'opt ... < %s' so that opt does not emit a ↵Dmitri Gribenko2013-01-221-1/+1
| | | | | | | | | ModuleID This is done to avoid odd test failures, like the one fixed in r171243. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173163 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Do not insert check on volatile store.Evgeniy Stepanov2013-01-221-0/+14
| | | | | | | Volatile bitfields can cause valid stores of uninitialized bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173153 91177308-0d34-0410-b5e6-96231b3b80d8
* This test is only supposed to test that the objc-arc alias analysisMichael Gottesman2013-01-221-1/+1
| | | | | | | allows for gvn to perform certain optimizations. Thus the runline should only contain -objc-arc-aa, not the full -objc-arc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173126 91177308-0d34-0410-b5e6-96231b3b80d8
* [MC/Mach-O] Load commands are supposed to 8-byte aligned on 64-bit.Daniel Dunbar2013-01-221-1/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173120 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove target triple from an LSR test.Andrew Trick2013-01-221-1/+0
| | | | | | Manish already fixed this test to work with NoTTI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173110 91177308-0d34-0410-b5e6-96231b3b80d8
* Transform (sub 0, (zext bool to A)) to (sext bool to A) andPaul Redmond2013-01-213-4/+12
| | | | | | | | | | (sub 0, (sext bool to A)) to (zext bool to A). Patch by Muhammad Ahmad Reviewed by Duncan Sands git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173093 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction encodings / disassembly support for u6 / lu6 instructions.Richard Osborne2013-01-211-0/+50
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173086 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction encoding / disassembly support for ru6 / lru6 instructions.Richard Osborne2013-01-211-0/+80
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173085 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction encodings / disassembly support for l2rus instructions.Richard Osborne2013-01-201-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172987 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction encodings / disassembly support for l3r instructions.Richard Osborne2013-01-201-0/+44
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172986 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction encodings / disassembler support for 2rus instructions.Richard Osborne2013-01-201-0/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172985 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction encodings / disassembly support 3r instructions.Richard Osborne2013-01-201-0/+38
| | | | | | | | It is not possible to distinguish 3r instructions from 2r / rus instructions using only the fixed bits. Therefore if an instruction doesn't match the 2r / rus format try to decode it as a 3r instruction before returning Fail. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/X86/win_ftol2.ll: Add -cpu=generic to appease valgrind.NAKAMURA Takumi2013-01-201-1/+1
| | | | | | | On valgrind the processor is reported; Host CPU: athlon-fx git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172983 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 172708.Nadav Rotem2013-01-202-68/+0
| | | | | | | | | | | The optimization handles esoteric cases but adds a lot of complexity both to the X86 backend and to other backends. This optimization disables an important canonicalization of chains of SEXT nodes and makes SEXT and ZEXT asymmetrical. Disabling the canonicalization of consecutive SEXT nodes into a single node disables other DAG optimizations that assume that there is only one SEXT node. The AVX mask optimizations is one example. Additionally this optimization does not update the cost model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172968 91177308-0d34-0410-b5e6-96231b3b80d8
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