aboutsummaryrefslogtreecommitdiffstats
path: root/test
Commit message (Collapse)AuthorAgeFilesLines
...
* PR16490: fix a crash in ARMDAGToDAGISel::SelectInlineAsm.Joey Gouly2013-07-051-0/+5
| | | | | | | | | | | | In the SelectionDAG immediate operands to inline asm are constructed as two separate operands. The first is a constant of value InlineAsm::Kind_Imm and the second is a constant with the value of the immediate. In ARMDAGToDAGISel::SelectInlineAsm, if we reach an operand of Kind_Imm we should skip over the next operand too. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185688 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: (icmp eq B, 0) | (icmp ult A, B) -> (icmp ule A, B-1)David Majnemer2013-07-051-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This transform allows us to turn IR that looks like: %1 = icmp eq i64 %b, 0 %2 = icmp ult i64 %a, %b %3 = or i1 %1, %2 ret i1 %3 into: %0 = add i64 %b, -1 %1 = icmp uge i64 %0, %a ret i1 %1 which means we go from lowering: cmpq %rsi, %rdi setb %cl testq %rsi, %rsi sete %al orb %cl, %al ret to lowering: decq %rsi cmpq %rdi, %rsi setae %al ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185677 91177308-0d34-0410-b5e6-96231b3b80d8
* DebugInfo: Consider global variables without locations to be validDavid Blaikie2013-07-041-0/+38
| | | | | | | | | | | | | | | | | We were being a bit too aggresive here in classifying global variables with no global reference or constant value to be invalid - this would cause LLVM to not emit the DWARF description of the global variable if it had been optimized away, which isn't helpful for users who might benefit from the global variable's description even if there's no location information. This also fixes a crasher issue here that I was unable to reduce a test case for - involving a using decl (& subsequent DW_TAG_imported_declaration ) of such a global variable that, once optimized away, would crash when an attempt to emit the imported declaration was made. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185675 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Add .section directive to COFFNico Rieck2013-07-043-2/+178
| | | | | | | | Supports GAS flags "abdnrswxy". No support for alignment or subsections. Fixes PR16366. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185669 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Reimplementation of visitUDivOperandDavid Majnemer2013-07-041-1/+0
| | | | | | | | | | | | This transform was originally added in r185257 but later removed in r185415. The original transform would create instructions speculatively and then discard them if the speculation was proved incorrect. This has been replaced with a scheme that splits the transform into two parts: preflight and fold. While we preflight, we build up fold actions that inform the folding stage on how to act. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185667 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for archives with no symbol table or string table.Rafael Espindola2013-07-042-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185664 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Implement writeNopDataUlrich Weigand2013-07-041-0/+9
| | | | | | | | | | | | | This implements a proper PPCAsmBackend::writeNopData routine that actually writes PowerPC nop instructions. This fixes the last remaining difference in object file output (text section) between the integrated assembler and GNU as that I've seen anywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185662 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 'not' in front of a command that is expected to fail.Rafael Espindola2013-07-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185659 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} ↵Joey Gouly2013-07-042-0/+43
| | | | | | | | | | instructions. This adds a new decoder table/namespace 'VFPV8', as these instructions have their top 4 bits as 0b1111, while other Thumb instructions have 0b1110. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185642 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Add all trap mnemonicsUlrich Weigand2013-07-042-2/+149
| | | | | | | | | This adds support for all basic and extended variants of the trap instructions to the asm parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185638 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Add asm parser support for CR expressionsUlrich Weigand2013-07-041-1/+99
| | | | | | | | | | This adds support for specifying condition registers and condition register fields via expressions using the symbols defined by the PowerISA, like "4*cr2+eq". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185633 91177308-0d34-0410-b5e6-96231b3b80d8
* SimplifyCFG: Teach switch generation some patterns that instcombine forms.Benjamin Kramer2013-07-041-0/+36
| | | | | | | | This allows us to create switches even if instcombine has munged two of the incombing compares into one and some bit twiddling. This was motivated by enum compares that are common in clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185632 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a V8FP instruction 'vcvt{b,t}' to convert between half and double precision.Joey Gouly2013-07-044-0/+68
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185620 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Improve the instruction selection of vector loads.Quentin Colombet2013-07-032-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | In the ARM back-end, build_vector nodes are lowered to a target specific build_vector that uses floating point type. This works well, unless the inserted bitcasts survive until instruction selection. In that case, they incur moves between integer unit and floating point unit that may result in inefficient code. In other words, this conversion may introduce artificial dependencies when the code leading to the build vector cannot be completed with a floating point type. In particular, this happens when loads are not aligned. Before this patch, in that case, the compiler generates general purpose loads and creates the floating point vector from them, instead of directly using the vector unit. The patch uses a vector friendly sequence of code when the inserted bitcasts to floating point survived DAGCombine. This is done by a target specific DAGCombine that changes the target specific build_vector into a sequence of insert_vector_elt that get rid of the bitcasts. <rdar://problem/14170854> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185587 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Prevent ARMAsmParser::shouldOmitCCOutOperand() from misidentifying ↵Tilmann Scheller2013-07-031-0/+2
| | | | | | | | | | | | | | | | certain Thumb2 add immediate T3 encodings. Before the fix Thumb2 instructions of type "add rD, rN, #imm" (T3 encoding, see ARM ARM A8.8.4) with rD and rN both being low registers (r0-r7) were classified as having the T4 encoding. The T4 encoding doesn't have a cc_out operand so for above instructions the operand gets erroneously removed, corrupting the token stream and leading to parse errors later in the process. This bug prevented "add r1, r7, #0xcbcbcbcb" from being assembled correctly. Fixes <rdar://problem/14224440>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185575 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support lmw/stmw in the asm parserUlrich Weigand2013-07-031-1/+6
| | | | | | | | | This adds support for the load/store multiple instructions, currently used by the asm parser only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185564 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Use mtocrf when availableUlrich Weigand2013-07-033-14/+16
| | | | | | | | | | | | | | | | | | | | | | Just as with mfocrf, it is also preferable to use mtocrf instead of mtcrf when only a single CR register is to be written. Current code however always emits mtcrf. This probably does not matter when using an external assembler, since the GNU assembler will in fact automatically replace mtcrf with mtocrf when possible. It does create inefficient code with the integrated assembler, however. To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and uses those instead of MTCRF/MTCRF8 everything. Just as done in the MFOCRF patch committed as 185556, these patterns will be converted back to MTCRF if MTOCRF is not available on the machine. As a side effect, this allows to modify the MTCRF pattern to accept the full range of mask operands for the benefit of the asm parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185561 91177308-0d34-0410-b5e6-96231b3b80d8
* Prefix failing commands with not to make clear they are expected to fail.Rafael Espindola2013-07-0326-30/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185554 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove another old test.Rafael Espindola2013-07-031-99/+0
| | | | | | | It was only passing because 'grep andpd' was not finding any andpd, but we don't fail if part of a pipe fails. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185552 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove test for the old EH system. It doesn't parse anymore.Rafael Espindola2013-07-031-19/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185551 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix test: It was missing run lines and llvm-dis has no -disable-verify option.Rafael Espindola2013-07-031-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185550 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for gnu archives with a string table and no symtab.Rafael Espindola2013-07-032-0/+8
| | | | | | While there, use early returns to reduce nesting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185547 91177308-0d34-0410-b5e6-96231b3b80d8
* Make llvm-nm return 1 on error.Rafael Espindola2013-07-031-0/+17
| | | | | | | This is a small compatibility improvement with gnu nm and makes llvm-nm more useful as a testing tool. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185546 91177308-0d34-0410-b5e6-96231b3b80d8
* [msan] Unpoison stack allocations and undef values in blacklisted functions.Evgeniy Stepanov2013-07-031-0/+35
| | | | | | | | | This changes behavior of -msan-poison-stack=0 flag from not poisoning stack allocations to actively unpoisoning them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185538 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support mtspr/mfspr in the asm parserUlrich Weigand2013-07-032-4/+8
| | | | | | | | | | | This adds support for the generic forms of mtspr/mfspr for the asm parser. The compiler will continue to use the specialized patters for mtlr etc. since those are needed to correctly describe data flow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185532 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Fold more spillsRichard Sandiford2013-07-0355-0/+3654
| | | | | | | | | | | | | | | | Add a mapping from register-based <INSN>R instructions to the corresponding memory-based <INSN>. Use it to cut down on the number of spill loads. Some instructions extend their operands from smaller fields, so this required a new TSFlags field to say how big the unextended operand is. This optimisation doesn't trigger for C(G)R and CL(G)R because in practice we always combine those instructions with a branch. Adding a test for every other case probably seems excessive, but it did catch a missed optimisation for DSGF (fixed in r185435). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185529 91177308-0d34-0410-b5e6-96231b3b80d8
* This corrects the implementation of Thumb ADR instruction. There are three ↵Mihai Popa2013-07-033-6/+16
| | | | | | | | | | | issues: 1. it should accept only 4-byte aligned addresses 2. the maximum offset should be 1020 3. it should be encoded with the offset scaled by two bits git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185528 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: relax the atomic release barrier to "dmb ishst" on SwiftTim Northover2013-07-033-56/+101
| | | | | | | | | | | Swift cores implement store barriers that are stronger than the ARM specification but weaker than general barriers. They are, in fact, just about enough to provide the ordering needed for atomic operations with release semantics. This patch makes use of that quirk. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185527 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add ISel pattern for LDWCPRichard Osborne2013-07-031-0/+9
| | | | | | Patch by Robert Lytton. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185518 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the gettimeofday test to only test on a posix platform.Michael Gottesman2013-07-031-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185503 91177308-0d34-0410-b5e6-96231b3b80d8
* Added support in FunctionAttrs for adding relevant function/argument ↵Michael Gottesman2013-07-031-0/+3
| | | | | | | | | | attributes for the posix call gettimeofday. This implies annotating it as nounwind and its arguments as nocapture. To be conservative, we do not annotate the arguments with noalias since some platforms do not have restrict on the declaration for gettimeofday. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185502 91177308-0d34-0410-b5e6-96231b3b80d8
* Trying to fix the botsManman Ren2013-07-031-2/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185489 91177308-0d34-0410-b5e6-96231b3b80d8
* Debug Info: use module flag to set up Dwarf version.Manman Ren2013-07-021-0/+27
| | | | | | | | | | Correctly handles ref_addr depending on the Dwarf version. Emit Dwarf with version from module flag. TODO: turn on/off features depending on the Dwarf version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185484 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] PR16512 - Support TLS call sequences in the asm parserUlrich Weigand2013-07-021-0/+14
| | | | | | | | | | | This patch now adds support for recognizing TLS call sequences in the asm parser. This needs a new pattern BL8_TLS, which is like BL8_NOP_TLS except without nop. That pattern is used for the asm parser only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185478 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Remove VK_PPC_TLSGD and VK_PPC_TLSLDUlrich Weigand2013-07-023-3/+3
| | | | | | | | | | | | | | | | | The PowerPC-specific modifiers VK_PPC_TLSGD and VK_PPC_TLSLD correspond exactly to the generic modifiers VK_TLSGD and VK_TLSLD. This causes some confusion with the asm parser, since VK_PPC_TLSGD is output as @tlsgd, which is then read back in as VK_TLSGD. To avoid this confusion, this patch removes the PowerPC-specific modifiers and uses the generic modifiers throughout. (The only drawback is that the generic modifiers are printed in upper case while the usual convention on PowerPC is to use lower-case modifiers. But this is just a cosmetic issue.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185476 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 'REQUIRES: object-emission' to DebugInfo/inlined-arguments.ll.Jyotsna Verma2013-07-021-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185465 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support TLS variables in debug infoUlrich Weigand2013-07-022-3/+40
| | | | | | | | | | | This adds an implementation of getDebugThreadLocalSymbol for (64-bit) PowerPC. This needs to return a generic MCExpr since on ppc64, we need to add a bias of 0x8000 to the value returned by the R_PPC64_DTPREL64 relocation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185461 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Use DSGFR over DSGR in more casesRichard Sandiford2013-07-022-0/+37
| | | | | | | | | | | Fixes some cases where we were using full 64-bit division for (sdiv i32, i32) and (sdiv i64, i32). The "32" in "SDIVREM32" just refers to the second operand. The first operand of all *DIVREM*s is a GR128. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185435 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Use MVC to spill loads and storesRichard Sandiford2013-07-023-0/+469
| | | | | | | | | | | | | | | | | | | | | | Try to use MVC when spilling the destination of a simple load or the source of a simple store. As explained in the comment, this doesn't yet handle the case where the load or store location is also a frame index, since that could lead to two simultaneous scavenger spills, something the backend can't handle yet. spill-02.py tests that this restriction kicks in, but unfortunately I've not yet found a case that would fail without it. The volatile trick I used for other scavenger tests doesn't work here because we can't use MVC for volatile accesses anyway. I'm planning on relaxing the restriction later, hopefully with a test that does trigger the problem... Tests @f8 and @f9 also showed that L(G)RL and ST(G)RL were wrongly classified as SimpleBDX{Load,Store}. It wouldn't be easy to test for that bug separately, which is why I didn't split out the fix as a separate patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185434 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Add the MVC instructionRichard Sandiford2013-07-023-3/+82
| | | | | | | | | | This is the first use of D(L,B) addressing, which required a fair bit of surgery. For that reason, the patch just adds the instruction definition and the associated assembler and disassembler support. A later patch will actually make use of it for codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185433 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Fix instruction selection for zext, mkmsk instructions.Richard Osborne2013-07-022-0/+18
| | | | | | | | | | | r182680 replaced CountLeadingZeros_32 with a template function countLeadingZeros that relies on using the correct argument type to give the right result. The type passed in the XCore backend after this revision was incorrect in a couple of places. Patch by Robert Lytton. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185430 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM EHABI compact model 1 and 2 without handlerdata.Logan Chien2013-07-021-1/+1
| | | | | | | | | | | | | | | | According to ARM EHABI section 9.2, if the __aeabi_unwind_cpp_pr1() or __aeabi_unwind_cpp_pr2() is used, then the handler data must be emitted after the unwind opcodes. The handler data consists of several words, and should be terminated by zero. In case that the .handlerdata directive is not specified by the programmer, we should emit zero to terminate the handler data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185422 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGCombiner: fix use-counting issue when forming zextloadTim Northover2013-07-021-0/+16
| | | | | | | | | | DAGCombiner was counting all uses of a load node when considering whether it's worth combining into a zextload. Really, it wants to ignore the chain and just count real uses. rdar://problem/13896307 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185419 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r185257 (InstCombine: Be more agressive optimizing 'udiv' instrs with ↵Hal Finkel2013-07-022-0/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'select' denoms) I'm reverting this commit because: 1. As discussed during review, it needs to be rewritten (to avoid creating and then deleting instructions). 2. This is causing optimizer crashes. Specifically, I'm seeing things like this: While deleting: i1 % Use still stuck around after Def is destroyed: <badref> = select i1 <badref>, i32 0, i32 1 opt: /src/llvm-trunk/lib/IR/Value.cpp:79: virtual llvm::Value::~Value(): Assertion `use_empty() && "Uses remain when a value is destroyed!"' failed. I'd guess that these will go away once we're no longer creating/deleting instructions here, but just in case, I'm adding a regression test. Because the code is bring rewritten, I've just XFAIL'd the original regression test. Original commit message: InstCombine: Be more agressive optimizing 'udiv' instrs with 'select' denoms Real world code sometimes has the denominator of a 'udiv' be a 'select'. LLVM can handle such cases but only when the 'select' operands are symmetric in structure (both select operands are a constant power of two or a left shift, etc.). This falls apart if we are dealt a 'udiv' where the code is not symetric or if the select operands lead us to more select instructions. Instead, we should treat the LHS and each select operand as a distinct divide operation and try to optimize them independently. If we can to simplify each operation, then we can replace the 'udiv' with, say, a 'lshr' that has a new select with a bunch of new operands for the select. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185415 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handlingHal Finkel2013-07-022-0/+269
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a couple of (small) related changes here: 1. The printed name of the VRSAVE register has been changed from VRsave to vrsave in order to match the name accepted by GNU binutils. 2. Support for parsing vrsave has been added to the asm parser (it seems that there was no test case specifically covering this code, so I've added one). 3. The list of Altivec registers, which was common to all calling conventions, has been separated out. This allows us to define the base CSR lists, and then lists for each ABI with Altivec included. This allows SjLj, for example, to work correctly on non-Altivec targets without using unnatural definitions of the NoRegs CSR list. 4. VRSAVE is now always reserved on non-Darwin targets and all Altivec registers are reserved when Altivec is disabled. With these changes, it is now possible to compile a function containing __builtin_unwind_init() on Linux/PPC64 with debugging information. This did not work previously because GNU binutils assumes that all .cfi_offset offsets will be 8-byte aligned on PPC64 (and errors out if you provide a non-8-byte-aligned offset). This is not true for the vrsave register, however, because this register is used only on Darwin, GCC does not bother printing a .cfi_offset entry for it (even though there is a slot in the stack frame for it as specified by the ABI). This change allows us to do the same: we will also not print .cfi_offset directives for vrsave. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185409 91177308-0d34-0410-b5e6-96231b3b80d8
* PR14728: DebugInfo: TLS variables with -gsplit-dwarfDavid Blaikie2013-07-011-0/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185398 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Add support for TLS data relocationsUlrich Weigand2013-07-011-2/+19
| | | | | | | | | | | | This adds support for TLS data relocations and modifiers: .quad target@dtpmod .quad target@tprel .quad target@dtprel Currently exploited by the asm parser only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185394 91177308-0d34-0410-b5e6-96231b3b80d8
* PR16493: DebugInfo with TLS on PPC crashing due to invalid relocationDavid Blaikie2013-07-013-2/+29
| | | | | | | | Restrict the current TLS support to X86 ELF for now. Test that we don't produce it on PPC & we can flesh that test case out with the right thing once someone implements it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185389 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support all condition register logical instructionsUlrich Weigand2013-07-012-7/+22
| | | | | | | | | This adds support for all missing condition register logical instructions and extended mnemonics to the asm parser. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185387 91177308-0d34-0410-b5e6-96231b3b80d8
* Index: test/CodeGen/PowerPC/reloc-align.llBill Schmidt2013-07-011-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | =================================================================== --- test/CodeGen/PowerPC/reloc-align.ll (revision 0) +++ test/CodeGen/PowerPC/reloc-align.ll (revision 0) @@ -0,0 +1,34 @@ +; RUN: llc -mcpu=pwr7 -O1 < %s | FileCheck %s + +; This test verifies that the peephole optimization of address accesses +; does not produce a load or store with a relocation that can't be +; satisfied for a given instruction encoding. Reduced from a test supplied +; by Hal Finkel. + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.S1 = type { [8 x i8] } + +@main.l_1554 = internal global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 -1, i8 -6, i8 57, i8 62, i8 -48, i8 0, i8 58, i8 80 }, align 1 + +; Function Attrs: nounwind readonly +define signext i32 @main() #0 { +entry: + %call = tail call fastcc signext i32 @func_90(%struct.S1* byval bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*)) +; CHECK-NOT: ld {{[0-9]+}}, main.l_1554@toc@l + ret i32 %call +} + +; Function Attrs: nounwind readonly +define internal fastcc signext i32 @func_90(%struct.S1* byval nocapture %p_91) #0 { +entry: + %0 = bitcast %struct.S1* %p_91 to i64* + %bf.load = load i64* %0, align 1 + %bf.shl = shl i64 %bf.load, 26 + %bf.ashr = ashr i64 %bf.shl, 54 + %bf.cast = trunc i64 %bf.ashr to i32 + ret i32 %bf.cast +} + +attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } Index: lib/Target/PowerPC/PPCAsmPrinter.cpp =================================================================== --- lib/Target/PowerPC/PPCAsmPrinter.cpp (revision 185327) +++ lib/Target/PowerPC/PPCAsmPrinter.cpp (working copy) @@ -679,7 +679,26 @@ void PPCAsmPrinter::EmitInstruction(const MachineI OutStreamer.EmitRawText(StringRef("\tmsync")); return; } + break; + case PPC::LD: + case PPC::STD: + case PPC::LWA: { + // Verify alignment is legal, so we don't create relocations + // that can't be supported. + // FIXME: This test is currently disabled for Darwin. The test + // suite shows a handful of test cases that fail this check for + // Darwin. Those need to be investigated before this sanity test + // can be enabled for those subtargets. + if (!Subtarget.isDarwin()) { + unsigned OpNum = (MI->getOpcode() == PPC::STD) ? 2 : 1; + const MachineOperand &MO = MI->getOperand(OpNum); + if (MO.isGlobal() && MO.getGlobal()->getAlignment() < 4) + llvm_unreachable("Global must be word-aligned for LD, STD, LWA!"); + } + // Now process the instruction normally. + break; } + } LowerPPCMachineInstrToMCInst(MI, TmpInst, *this); OutStreamer.EmitInstruction(TmpInst); Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp =================================================================== --- lib/Target/PowerPC/PPCISelDAGToDAG.cpp (revision 185327) +++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp (working copy) @@ -1530,6 +1530,14 @@ void PPCDAGToDAGISel::PostprocessISelDAG() { if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) { SDLoc dl(GA); const GlobalValue *GV = GA->getGlobal(); + // We can't perform this optimization for data whose alignment + // is insufficient for the instruction encoding. + if (GV->getAlignment() < 4 && + (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD || + StorageOpcode == PPC::LWA)) { + DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n"); + continue; + } ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags); } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(ImmOpnd)) { git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185380 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-02-13 15:35:31 +0000