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* [PowerPC] Always use "assembler dialect" 1Ulrich Weigand2013-07-081-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A setting in MCAsmInfo defines the "assembler dialect" to use. This is used by common code to choose between alternatives in a multi-alternative GNU inline asm statement like the following: __asm__ ("{sfe|subfe} %0,%1,%2" : "=r" (out) : "r" (in1), "r" (in2)); The meaning of these dialects is platform specific, and GCC defines those for PowerPC to use dialect 0 for old-style (POWER) mnemonics and 1 for new-style (PowerPC) mnemonics, like in the example above. To be compatible with inline asm used with GCC, LLVM ought to do the same. Specifically, this means we should always use assembler dialect 1 since old-style mnemonics really aren't supported on any current platform. However, the current LLVM back-end uses: AssemblerDialect = 1; // New-Style mnemonics. in PPCMCAsmInfoDarwin, and AssemblerDialect = 0; // Old-Style mnemonics. in PPCLinuxMCAsmInfo. The Linux setting really isn't correct, we should be using new-style mnemonics everywhere. This is changed by this commit. Unfortunately, the setting of this variable is overloaded in the back-end to decide whether or not we are on a Darwin target. This is done in PPCInstPrinter (the "SyntaxVariant" is initialized from the MCAsmInfo AssemblerDialect setting), and also in PPCMCExpr. Setting AssemblerDialect to 1 for both Darwin and Linux no longer allows us to make this distinction. Instead, this patch uses the MCSubtargetInfo passed to createPPCMCInstPrinter to distinguish Darwin targets, and ignores the SyntaxVariant parameter. As to PPCMCExpr, this patch adds an explicit isDarwin argument that needs to be passed in by the caller when creating a target MCExpr. (To do so this patch implicitly also reverts commit 184441.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185858 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC: Mark vector CC action for SETO and SETONE as ExpandHal Finkel2013-07-081-0/+17
| | | | | | | | Another bug found by llvm-stress! This fixes hitting llvm_unreachable("Invalid integer vector compare condition"); at the end of getVCmpInst in PPCISelDAGToDAG. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185855 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a comment to this change, requested by Eric Christopher.Joey Gouly2013-07-081-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185853 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Improve codegen for generic vselect.Jim Grosbach2013-07-082-30/+39
| | | | | | | | Fall back to by-element insert rather than building it up on the stack. rdar://14351991 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185846 91177308-0d34-0410-b5e6-96231b3b80d8
* PPC: Mark vector FREM as Expand by defaultHal Finkel2013-07-081-0/+8
| | | | | | | Another bug found by llvm-stress! This fixes crashing with: LLVM ERROR: Cannot select: v4f32 = frem ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185840 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support time base instructionsUlrich Weigand2013-07-081-0/+9
| | | | | | | | | | This adds support for the old-style time base instructions; while new programs are supposed to use mfspr, the mftb instructions are still supported and in use by existing assembler files. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185829 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support basic compare mnemonicsUlrich Weigand2013-07-081-1/+19
| | | | | | | | | | | | | | | | | | | This adds support for the basic mnemoics (with the L operand) for the fixed-point compare instructions. These are defined as aliases for the already existing CMPW/CMPD patterns, depending on the value of L. This requires use of InstAlias patterns with immediate literal operands. To make this work, we need two further changes: - define a RegisterPrefix, because otherwise literals 0 and 1 would be parsed as literal register names - provide a PPCAsmParser::validateTargetOperandClass routine to recognize immediate literals (like ARM does) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185826 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Fix PR16556 (handle undef ppcf128 in LowerFP_TO_INT).Bill Schmidt2013-07-081-0/+20
| | | | | | | | | | | | | | | | | | | | | | PPCTargetLowering::LowerFP_TO_INT() expects its source operand to be either an f32 or f64, but this is not checked. A long double (ppcf128) operand will normally be custom-lowered to a conversion to f64 in this context. However, this isn't the case for an UNDEF node. This patch recognizes a ppcf128 as a legal source operand for FP_TO_INT only if it's an undef, in which case it creates an undef of the target type. At some point we might want to do a wholesale custom lowering of ISD::UNDEF when the type is ppcf128, but it's not really clear that's a great idea, and probably more work than it's worth for a situation that only arises in the case of a programming error. At this point I think simple is best. The test case comes from PR16556, and is a crash-test only. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185821 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert an OCaml binding grep test to FileCheckReid Kleckner2013-07-081-329/+340
| | | | | | | | I shaved this yak because I mistakenly thought that this was one of the last grep tests. Turns out my search was skipping .ll files, for which there are ~1200 more tests using grep. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185819 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Fold X-C1 <u 2 -> (X & -2) == C1David Majnemer2013-07-081-0/+10
| | | | | | | | | | | | Back in r179493 we determined that two transforms collided with each other. The fix back then was to reorder the transforms so that the preferred transform would give it a try and then we would try the secondary transform. However, it was noted that the best approach would canonicalize one transform into the other, removing the collision and allowing us to optimize IR given to us in that form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185808 91177308-0d34-0410-b5e6-96231b3b80d8
* Reuse %rax after calling __chkstk on win64Nico Rieck2013-07-081-1/+1
| | | | | | Reapply this as I reverted the wrong commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185807 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Proper va_arg/va_copy lowering on win64"Nico Rieck2013-07-081-59/+0
| | | | | | | | This reverts commit 2b52880592a525cfe04d8f9008a35da8c2ea94c3. Needs review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185806 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Use MVC for memcpyRichard Sandiford2013-07-081-0/+82
| | | | | | | | Use MVC for memcpy in cases where a single MVC is enough. Using MVC is a win for longer copies too, but I'll leave that for later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185802 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CMakeLists.txt: Add llvm-cov in "check-clang".NAKAMURA Takumi2013-07-081-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185801 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CMakeLists.txt: Reformat LLVM_TEST_DEPENDS.NAKAMURA Takumi2013-07-081-8/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185800 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/Other/llvm-cov.test: It requires +Asserts to let XFAILed.NAKAMURA Takumi2013-07-081-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185799 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PromoteIntRes_BUILD_VECTOR crash with i1 vectorsHal Finkel2013-07-081-0/+39
| | | | | | | | | | | | | This fixes a bug (found by llvm-stress) in DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR where it assumed that the result type would always be larger than the original operands. This is not always true, however, with boolean vectors. For example, promoting a node of type v8i1 (where the operands will be of type i32, the type to which i1 is promoted) will yield a node with a result vector element type of i16 (and operands of type i32). As a result, we cannot blindly assume that we can ANY_EXTEND the operands to the result type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185794 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert: Fix wrong code offset for unwind code SET_FPREG.Kai Nacke2013-07-082-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185793 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert: Generate IMAGE_REL_AMD64_ADDR32NB relocations for SEH data structures.Kai Nacke2013-07-082-32/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185791 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert: Fix alignment of unwind data.Kai Nacke2013-07-083-226/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185790 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the nearbyint -> FNEARBYINT mapping to BasicTargetTransformInfoHal Finkel2013-07-081-0/+28
| | | | | | | | This fixes an oversight that Intrinsic::nearbyint was not being mapped to ISD::FNEARBYINT (thus fixing the over-optimistic cost we were assigning to nearbyint calls for some targets). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185783 91177308-0d34-0410-b5e6-96231b3b80d8
* [objc-arc] Committed test for r185770 as per dblaikie's suggestion.Michael Gottesman2013-07-081-0/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185782 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Reuse %rax after calling __chkstk on win64"Nico Rieck2013-07-081-1/+1
| | | | | | This reverts commit 01f8d579f7672872324208ac5bc4ac311e81b22e. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185781 91177308-0d34-0410-b5e6-96231b3b80d8
* Reuse %rax after calling __chkstk on win64Nico Rieck2013-07-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185778 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate trivial redundant loads across nocapture+readonly calls to uncapturedNick Lewycky2013-07-071-0/+17
| | | | | | | pointer arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185776 91177308-0d34-0410-b5e6-96231b3b80d8
* SLPVectorizer: Implement DCE as part of vectorization.Nadav Rotem2013-07-0716-8/+645
| | | | | | | | | | | This is a complete re-write if the bottom-up vectorization class. Before this commit we scanned the instruction tree 3 times. First in search of merge points for the trees. Second, for estimating the cost. And finally for vectorization. There was a lot of code duplication and adding the DCE exposed bugs. The new design is simpler and DCE was a part of the design. In this implementation we build the tree once. After that we estimate the cost by scanning the different entries in the constructed tree (in any order). The vectorization phase also works on the built tree. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185774 91177308-0d34-0410-b5e6-96231b3b80d8
* [objc-arc] Remove the alias analysis part of r185764.Michael Gottesman2013-07-071-18/+0
| | | | | | | Upon further reflection, the alias analysis part of r185764 is not a safe change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185770 91177308-0d34-0410-b5e6-96231b3b80d8
* [objc-arc] Teach the ARC optimizer that objc_sync_enter/objc_sync_exit do ↵Michael Gottesman2013-07-072-5/+42
| | | | | | not modify the ref count of an objc object and additionally are inert for modref purposes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185769 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MC support for the v8fp instructions: vmaxnm and vminnm.Joey Gouly2013-07-062-0/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185767 91177308-0d34-0410-b5e6-96231b3b80d8
* Proper va_arg/va_copy lowering on win64Nico Rieck2013-07-061-0/+59
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185763 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix alignment of unwind data.Kai Nacke2013-07-063-0/+226
| | | | | | | | | | | | For alignment purposes, the instruction array will always have an even number of entries, with the final entry potentially unused (in which case the array will be one longer than indicated by the count of unwind codes field). Reviewed by Charles Davis and Nico Rieck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185760 91177308-0d34-0410-b5e6-96231b3b80d8
* Generate IMAGE_REL_AMD64_ADDR32NB relocations for SEHKai Nacke2013-07-062-11/+32
| | | | | | | | | | | | | | | data structures. The Win64 EH data structures must be of type IMAGE_REL_AMD64_ADDR32NB instead of IMAGE_REL_AMD64_ADDR32. This is easiely achieved by adding the VK_COFF_IMGREL32 modifier to the symbol reference. Change also references to start and end of the SEH range of a function as offsets to start of the function. Reviewed by Charles Davis and Nico Rieck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185759 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix wrong code offset for unwind code SET_FPREG.Kai Nacke2013-07-062-3/+1
| | | | | | | | | | | | | The code offset for unwind code SET_FPREG is wrong because it is set to constant 0. The fix is to do the same as for the other unwind codes: emit a label and later the absolute difference between the label and the begin of the prologue. Also enables the failing test case MC/COFF/seh.s Reviewed by Charles Davis and Nico Rieck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185758 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGCombiner: Don't drop extension behavior when shrinking a load when unsafe.Benjamin Kramer2013-07-061-0/+23
| | | | | | | | | | | | ReduceLoadWidth unconditionally drops extensions from loads. Limit it to the case when all of the bits the extension would otherwise produce are dropped by the shrink. It would be possible to shrink the load in more cases by merging the extensions, but this isn't trivial and a very rare case. I left a TODO for that case. Fixes PR16551. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185755 91177308-0d34-0410-b5e6-96231b3b80d8
* Stop putting operations after a tail call.Tim Northover2013-07-061-0/+16
| | | | | | | | This prevents the emission of DAG-generated vreg definitions after a tail call be dropping them entirely (on the grounds that nothing could use them anyway, and they interfere with O0 CodeGen). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185754 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Implement COFF .linkonce directiveNico Rieck2013-07-062-0/+219
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185753 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: typo in or_icmp_eq_B_0_icmp_ult_A_B testDavid Majnemer2013-07-061-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185737 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend 'readonly' and 'readnone' to work on function arguments as well asNick Lewycky2013-07-068-22/+80
| | | | | | | | functions. Make the function attributes pass add it to known library functions and when it can deduce it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185735 91177308-0d34-0410-b5e6-96231b3b80d8
* [TRE] Combined another test into basic.llMichael Gottesman2013-07-052-13/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185729 91177308-0d34-0410-b5e6-96231b3b80d8
* [TRE] Merged several tests into the the test basic.ll.Michael Gottesman2013-07-055-62/+58
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185723 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Add a pack pattern for matching arithmetic shift rightArnold Schwaighofer2013-07-051-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185714 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Fix incorrect pack patternArnold Schwaighofer2013-07-051-1/+14
| | | | | | | | | | | A "pkhtb x, x, y asr #num" uses the lower 16 bits of "y asr #num" and packs them in the bottom half of "x". An arithmetic and logic shift are only equivalent in this context if the shift amount is 16. We would be shifting in ones into the bottom 16bits instead of zeros if "y" is negative. radar://14338767 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185712 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Remove no-op MVCsRichard Sandiford2013-07-051-0/+89
| | | | | | | | | | | | The stack coloring pass has code to delete stores and loads that become trivially dead after coloring. Extend it to cope with single instructions that copy from one frame index to another. The testcase happens to show an example of this kicking in at the moment. It did occur in Real Code too though. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185705 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix double renaming bug in stack coloring passRichard Sandiford2013-07-051-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The stack coloring pass renumbered frame indexes with a loop of the form: for each frame index FI for each instruction I that uses FI for each use of FI in I rename FI to FI' This caused problems if an instruction used two frame indexes F0 and F1 and if F0 was renamed to F1 and F1 to F2. The first time we visited the instruction we changed F0 to F1, then we changed both F1s to F2. In other words, the problem was that SSRefs recorded which instructions used an FI, but not which MachineOperands and MachineMemOperands within that instruction used it. This is easily fixed for MachineOperands by walking the instructions once and processing each operand in turn. There's already a loop to do that for dead store elimination, so it seemed more efficient to fuse the two at the block level. MachineMemOperands are more tricky because they can be shared between instructions. The patch handles them by making SSRefs an array of MachineMemOperands rather than an array of MachineInstrs. We might end up processing the same MachineMemOperand twice, but that's OK because we always know from the SSRefs index what the original frame index was. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185703 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Enable the use of MVC for frame-to-frame spillsRichard Sandiford2013-07-051-29/+56
| | | | | | | | | | | ...now that the problem that prompted the restriction has been fixed. The original spill-02.py was a compromise because at the time I couldn't find an example that actually failed without the two scavenging slots. The version included here did. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185701 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Add some special @got@tprel fixup casesUlrich Weigand2013-07-051-0/+20
| | | | | | | | | | | | | | | | | When a target@got@tprel or target@got@tprel@l symbol variant is used in a fixup_ppc_half16 (*not* fixup_ppc_half16ds) context, we currently fail, since the corresponding R_PPC64_GOT_TPREL16 / R_PPC64_GOT_TPREL16_LO relocation types do not exist. However, since such symbol variants resolve to GOT offsets which are always 4-aligned, we can simply instead use the _DS variants of the relocation types, which *do* exist. The same applies for the @got@dtprel variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185700 91177308-0d34-0410-b5e6-96231b3b80d8
* [SystemZ] Allocate a second register scavenging slotRichard Sandiford2013-07-058-308/+308
| | | | | | | | | | | | | | This is another prerequisite for frame-to-frame MVC copies. I'll commit the patch that makes use of the slot separately. The downside of trying to test many corner cases with each of the available addressing modes is that a fair few tests need to account for the new frame layout. I do still think it's useful to have all these tests though, since it's something that wouldn't get much coverage otherwise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185698 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't create an archive if, for example, we are asked to print the index.Rafael Espindola2013-07-051-0/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185697 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Make test case buildable with GNU asUlrich Weigand2013-07-051-12/+7
| | | | | | | | | | | | | The ppc64-fixups.s test currently fails to build with GNU as, since it does not support plain symbols as arguments to li/lis. Rewrite the test for R_PPC64_ADDR16 and R_PPC64_REL16 to use lwz instead. Allowing the test case to be built with both LLVM and GNU as makes it easier to spot unwanted difference in the output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185694 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support @tls in the asm parserUlrich Weigand2013-07-052-2/+15
| | | | | | | | | | | | | | | | | | | | This adds support for the last missing construct to parse TLS-related assembler code: add 3, 4, symbol@tls The ADD8TLS currently hard-codes the @tls into the assembler string. This cannot be handled by the asm parser, since @tls is parsed as a symbol variant. This patch changes ADD8TLS to have the @tls suffix printed as symbol variant on output too, which allows us to remove the isCodeGenOnly marker from ADD8TLS. This in turn means that we can add a AsmOperand to accept @tls marked symbols on input. As a side effect, this means that the fixup_ppc_tlsreg fixup type is no longer necessary and can be merged into fixup_ppc_nofixup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185692 91177308-0d34-0410-b5e6-96231b3b80d8
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