aboutsummaryrefslogtreecommitdiffstats
path: root/test
Commit message (Collapse)AuthorAgeFilesLines
* SCEVExpander fixes. Affects LSR and indvars.Andrew Trick2012-01-201-0/+37
| | | | | | | | | | | | | | | | | LSR has gradually been improved to more aggressively reuse existing code, particularly existing phi cycles. This exposed problems with the SCEVExpander's sloppy treatment of its insertion point. I applied some rigor to the insertion point problem that will hopefully avoid an endless bug cycle in this area. Changes: - Always used properlyDominates to check safe code hoisting. - The insertion point provided to SCEV is now considered a lower bound. This is usually a block terminator or the use itself. Under no cirumstance may SCEVExpander insert below this point. - LSR is reponsible for finding a "canonical" insertion point across expansion of different expressions. - Robust logic to determine whether IV increments are in "expanded" form and/or can be safely hoisted above some insertion point. Fixes PR11783: SCEVExpander assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148535 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for selecting 256-bit PALIGNR.Craig Topper2012-01-201-0/+57
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148532 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a low-quality test which was failing on Windows; ↵Eli Friedman2012-01-201-23/+0
| | | | | | test/CodeGen/X86/sret.ll is a better test for the relevant behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148526 91177308-0d34-0410-b5e6-96231b3b80d8
* Support MSVC x86-32 sret convention. PR11688. Patch by Joe Groff.Eli Friedman2012-01-201-0/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148513 91177308-0d34-0410-b5e6-96231b3b80d8
* Set the "tail" flag on pattern-matched objc_storeStrong calls.Dan Gohman2012-01-192-2/+2
| | | | | | | rdar://10531041. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148490 91177308-0d34-0410-b5e6-96231b3b80d8
* Post process 'and', 'sub' instructions and select better encoding, if available.Devang Patel2012-01-191-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148489 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel syntax: There is no need to create unary expr for simple negative ↵Devang Patel2012-01-191-0/+4
| | | | | | displacement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148486 91177308-0d34-0410-b5e6-96231b3b80d8
* Post process 'xor', 'or' and 'cmp' instructions and select better encoding, ↵Devang Patel2012-01-191-0/+22
| | | | | | if available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148485 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit ARM EHABI unwinding instructions for 3 more Thumb instructions.Evgeniy Stepanov2012-01-191-0/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148473 91177308-0d34-0410-b5e6-96231b3b80d8
* Add testcase.Jim Grosbach2012-01-191-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148454 91177308-0d34-0410-b5e6-96231b3b80d8
* Space after punctuation.Nick Lewycky2012-01-191-14/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148451 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a TargetOption for disabling tail calls.Nick Lewycky2012-01-191-0/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148442 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 alternate syntax for LDR(literal) and friends.Jim Grosbach2012-01-181-0/+27
| | | | | | | | Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]". rdar://10250964 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148432 91177308-0d34-0410-b5e6-96231b3b80d8
* Process instructions after match to select alternative encoding which may be ↵Devang Patel2012-01-181-0/+24
| | | | | | more desirable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148431 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 relaxation for LDR(literal).Jim Grosbach2012-01-181-0/+13
| | | | | | | | | If the fixup is out of range for the Thumb1 instruction, relax it to the Thumb2 encoding instead. rdar://10711829 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148424 91177308-0d34-0410-b5e6-96231b3b80d8
* Use llvm.global_ctors to locate global constructors insteadDan Gohman2012-01-181-0/+2
| | | | | | | of recognizing them by name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148416 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in the type-legalization of vector integers. When we bitcast one ↵Nadav Rotem2012-01-181-0/+14
| | | | | | vector type to another, we must not bitcast the result if one type is widened while the other is promoted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148383 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case renameAndrew Trick2012-01-171-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148344 91177308-0d34-0410-b5e6-96231b3b80d8
* MC tweak symbol difference resolution for non-local symbols.Jim Grosbach2012-01-173-5/+7
| | | | | | | | | | | | | | | | When the non-local symbol in the expression is in the same fragment as the second symbol, the assembler can still evaluate the expression without needing a relocation. For example, on ARM: _foo: ldr lr, (_foo - 4) rdar://10348687 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148341 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up.Jim Grosbach2012-01-171-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148339 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel syntax: Fix parser match class to check memory operand size.Devang Patel2012-01-171-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148338 91177308-0d34-0410-b5e6-96231b3b80d8
* Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.Nadav Rotem2012-01-173-5/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148337 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel syntax: Parse "BYTE PTR [RDX + RCX]"Devang Patel2012-01-171-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148334 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new ObjC ARC optimization pass to eliminate unneededDan Gohman2012-01-171-0/+51
| | | | | | | autorelease push+pop pairs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148330 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel syntax: Do not unncessarily create plus expression for memory operand ↵Devang Patel2012-01-171-0/+2
| | | | | | displacement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148321 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel syntax: Ignore mnemonic aliases.Devang Patel2012-01-171-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148316 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove "XFAIL: arm" from test/ExecutionEngine/test-return.llEli Bendersky2012-01-171-1/+0
| | | | | | | | The test passes on ARM bots git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148315 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel syntax: Robustify memory operand parsing.Devang Patel2012-01-171-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148312 91177308-0d34-0410-b5e6-96231b3b80d8
* Additional ExecutionEngine tests, as part of bringing up the MCJIT on ELFEli Bendersky2012-01-177-0/+244
| | | | | | | | | | | implementation. Currently lit still executes ExecutionEngine tests with JIT (not MCJIT) by default. MCJIT tests can be executed manually by calling llvm-lit with --param jit_impl=mcjit git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148299 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix 11769.Nadav Rotem2012-01-171-1/+12
| | | | | | | | | | In CanXFormVExtractWithShuffleIntoLoad we assumed that EXTRACT_VECTOR_ELT can be later handled by the DAGCombiner. However, in some cases on AVX, the EXTRACT_VECTOR_ELT is legalized to EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which currently is not handled by the DAGCombiner. In this patch I added a check that we only extract from the XMM part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148298 91177308-0d34-0410-b5e6-96231b3b80d8
* LSR fix: broaden the check for loop preheaders.Andrew Trick2012-01-171-0/+113
| | | | | | | | It's becoming clear that LoopSimplify needs to unconditionally create loop preheaders. But that is a bigger fix. For now, continuing to hack LSR. Fixes rdar://10701050 "Cannot split an edge from an IndirectBrInst" assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148288 91177308-0d34-0410-b5e6-96231b3b80d8
* AggressiveAntiDepBreaker needs to skip debug values because a debug value ↵Hal Finkel2012-01-161-0/+40
| | | | | | does not have a corresponding SUnit git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148260 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure the non-SSE lowering for fences correctly clobbers EFLAGS. PR11768.Eli Friedman2012-01-161-0/+34
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148240 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding a basic ELF dynamic loader and MC-JIT for ELF. Functionality is ↵Eli Bendersky2012-01-1641-47/+76
| | | | | | | | | | currently basic and will be enhanced with future patches. Patch developed by Andy Kaylor and Daniel Malea. Reviewed on llvm-commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148231 91177308-0d34-0410-b5e6-96231b3b80d8
* [AVX] Optimize x86 VSELECT instructions using SimplifyDemandedBits.Nadav Rotem2012-01-151-0/+37
| | | | | | | | | | | | | We know that the blend instructions only use the MSB, so if the mask is sign-extended then we can convert it into a SHL instruction. This is a common pattern because the type-legalizer sign-extends the i1 type which is used by the LLVM-IR for the condition. Added a new optimization in SimplifyDemandedBits for SIGN_EXTEND_INREG -> SHL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148225 91177308-0d34-0410-b5e6-96231b3b80d8
* Relax the FileCheck assertion a bit -- all we really care about is thatChandler Carruth2012-01-151-1/+1
| | | | | | | we're loading from the global array, not how it is spelled in the asm. This should fix the MSVC bots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148214 91177308-0d34-0410-b5e6-96231b3b80d8
* FileCheck-ize a test, make it more specific to directly test the shiftChandler Carruth2012-01-151-10/+14
| | | | | | removal desired. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148213 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a corner case hit by redundant phi elimination running after LSR.Andrew Trick2012-01-141-0/+50
| | | | | | | Fixes PR11761: bad IR w/ redundant Phi elim git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148177 91177308-0d34-0410-b5e6-96231b3b80d8
* After r147827 and r147902, it's now possible for unallocatable registers to beEvan Cheng2012-01-141-0/+103
| | | | | | | | | | | | | | | | | | | | live across BBs before register allocation. This miscompiled 197.parser when a cmp + b are optimized to a cbnz instruction even though the CPSR def is live-in a successor. cbnz r6, LBB89_12 ... LBB89_12: ble LBB89_1 The fix consists of two parts. 1) Teach LiveVariables that some unallocatable registers might be liveouts so don't mark their last use as kill if they are. 2) ARM constantpool island pass shouldn't form cbz / cbnz if the conditional branch does not kill CPSR. rdar://10676853 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148168 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup test case by adding checks for test names.Chad Rosier2012-01-141-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148166 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test showing how the Leh_func_endN symbol is used.Rafael Espindola2012-01-141-0/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148161 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new test.Devang Patel2012-01-131-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148128 91177308-0d34-0410-b5e6-96231b3b80d8
* test/CodeGen/ARM/test-sharedidx.ll: Fix for -Asserts.NAKAMURA Takumi2012-01-131-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148107 91177308-0d34-0410-b5e6-96231b3b80d8
* Add patterns for v16i16 and v32i8 immAllZerosV to select VPXOR to match ↵Craig Topper2012-01-131-1/+1
| | | | | | v4i64 and v8i32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148106 91177308-0d34-0410-b5e6-96231b3b80d8
* DAGCombine's logic for forming pre- and post- indexed loads / stores were beingEvan Cheng2012-01-132-4/+99
| | | | | | | | | | | | | | | | | overly conservative. It was concerned about cases where it would prohibit folding simple [r, c] addressing modes. e.g. ldr r0, [r2] ldr r1, [r2, #4] => ldr r0, [r2], #4 ldr r1, [r2] Change the logic to look for such cases which allows it to form indexed memory ops more aggressively. rdar://10674430 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148086 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement proper ObjC ARC objc_retainBlock "escape" analysis, so thatDan Gohman2012-01-132-2/+155
| | | | | | | | | the optimizer doesn't eliminate objc_retainBlock calls which are needed for their side effect of copying blocks onto the heap. This implements rdar://10361249. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148076 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failureElena Demikhovsky2012-01-121-1/+9
| | | | | | | | | lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&& "Op 1 of shuffle should not be undef"' failed. Added a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148044 91177308-0d34-0410-b5e6-96231b3b80d8
* Add error-reporting tests for platforms that don't support segmented stacks.Rafael Espindola2012-01-121-0/+11
| | | | | | Patch by Brian Anderson. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148042 91177308-0d34-0410-b5e6-96231b3b80d8
* Support segmented stacks on 64-bit FreeBSD.Rafael Espindola2012-01-121-0/+52
| | | | | | | This patch uses tcb_spare field in the tcb structure to store info. Patch by Jyun-Yan You. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148041 91177308-0d34-0410-b5e6-96231b3b80d8
* Support segmented stacks on win32.Rafael Espindola2012-01-121-0/+50
| | | | | | | Uses the pvArbitrary slot of the TIB, which is reserved for applications. We only support frames with a static size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148040 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-02-09 06:40:46 +0000