aboutsummaryrefslogtreecommitdiffstats
path: root/test
Commit message (Collapse)AuthorAgeFilesLines
* PR9446: RecursivelyDeleteTriviallyDeadInstructions can delete the instructionEli Friedman2011-04-021-0/+32
| | | | | | | | | | | | | after the given instruction; make sure to handle that case correctly. (It's difficult to trigger; the included testcase involves a dead block, but I don't think that's a requirement.) While I'm here, get rid of the unnecessary warning about SimplifyInstructionsInBlock, since it should work correctly as far as I know. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128782 91177308-0d34-0410-b5e6-96231b3b80d8
* ptx: support setp's 4-operand formatChe-Liang Chiou2011-04-021-0/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128767 91177308-0d34-0410-b5e6-96231b3b80d8
* Do some peephole optimizations to remove pointless VMOVs from Neon to integerCameron Zwarich2011-04-021-0/+11
| | | | | | | | registers that arise from argument shuffling with the soft float ABI. These instructions are particularly slow on Cortex A8. This fixes one half of <rdar://problem/8674845>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128759 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a bug in disassembly of STR_POST, where the immediate is the second ↵Johnny Chen2011-04-021-0/+3
| | | | | | | | | | | operand in am2offset; instead of the second operand in addrmode_imm12. rdar://problem/9225289 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128757 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed MOVr for "should be" encoding bits for Inst{19-16} = 0b0000.Johnny Chen2011-04-011-0/+13
| | | | | | | rdar://problem/9224276 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128749 91177308-0d34-0410-b5e6-96231b3b80d8
* MOVs should have Inst{19-16} as 0b0000, otherwise, the instruction is ↵Johnny Chen2011-04-011-0/+17
| | | | | | | | | UNPREDICTABLE. rdar://problem/9224120 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128748 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the instruction table entries for AI1_adde_sube_s_irs multiclass ↵Johnny Chen2011-04-011-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | definition so that all the instruction have: let Inst{31-27} = 0b1110; // non-predicated Before, the ARM decoder was confusing: > 0x40 0xf3 0xb8 0x80 as: Opcode=16 Name=ADCSSrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcs pc, r8, r0, asr #6 since the cond field for ADCSSrs is a wild card, and so is ADCrs, with the ADCSSrs having Inst{20} as '1'. Now, the AR decoder behaves correctly: > 0x40 0xf3 0xb8 0x80 > END Executing command: /Volumes/data/lldb/llvm/Debug+Asserts/bin/llvm-mc -disassemble -triple=arm-apple-darwin -debug-only=arm-disassembler mc-input.txt Opcode=19 Name=ADCrs Format=ARM_FORMAT_DPSOREGFRM(5) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ------------------------------------------------------------------------------------------------- | 1: 0: 0: 0| 0: 0: 0: 0| 1: 0: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| ------------------------------------------------------------------------------------------------- adcshi pc, r8, r0, asr #6 > rdar://problem/9223094 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128746 91177308-0d34-0410-b5e6-96231b3b80d8
* LDRD/STRD instructions should print both Rt and Rt2 in the asm string.Jim Grosbach2011-04-012-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128736 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a LDRT/LDRBT decoding bug where for Encoding A2, if Inst{4} != 0, we ↵Johnny Chen2011-04-012-0/+15
| | | | | | | | | should reject the instruction as invalid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128734 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Turn icmp + sext into bitwise/integer ops when the input has ↵Benjamin Kramer2011-04-011-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | only one unknown bit. int test1(unsigned x) { return (x&8) ? 0 : -1; } int test3(unsigned x) { return (x&8) ? -1 : 0; } before (x86_64): _test1: andl $8, %edi cmpl $1, %edi sbbl %eax, %eax ret _test3: andl $8, %edi cmpl $1, %edi sbbl %eax, %eax notl %eax ret after: _test1: shrl $3, %edi andl $1, %edi leal -1(%rdi), %eax ret _test3: shll $28, %edi movl %edi, %eax sarl $31, %eax ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128732 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix LDRi12 immediate operand, which was changed to be the second operand in ↵Johnny Chen2011-04-011-0/+9
| | | | | | | | | $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm). rdar://problem/9219356 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128722 91177308-0d34-0410-b5e6-96231b3b80d8
* Add code for analyzing FP branches. Clean up branch Analysis functions.Akira Hatanaka2011-04-012-2/+48
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128718 91177308-0d34-0410-b5e6-96231b3b80d8
* Add test case.Evan Cheng2011-04-011-0/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128707 91177308-0d34-0410-b5e6-96231b3b80d8
* FileCheck'ify test.Evan Cheng2011-04-011-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128706 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Thumb and Thumb2 tests to be register allocator independent.Jakob Stoklund Olesen2011-03-315-23/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128690 91177308-0d34-0410-b5e6-96231b3b80d8
* Apply again changes to support ARM memory asm parsing. I removedBruno Cardoso Lopes2011-03-311-0/+34
| | | | | | | | | | | | | | all LDR/STR changes and left them to a future patch. Passing all checks now. - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and fix the encoding wherever is possible. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128689 91177308-0d34-0410-b5e6-96231b3b80d8
* Provide a legal pointer register class when targeting thumb1.Jakob Stoklund Olesen2011-03-311-1/+1
| | | | | | The LocalStackSlotAllocation pass was creating illegal registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128687 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix SystemZ testsJakob Stoklund Olesen2011-03-311-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128686 91177308-0d34-0410-b5e6-96231b3b80d8
* Instcombile optimization: extractelement(cast) -> cast(extractelement)Nadav Rotem2011-03-311-0/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128683 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ARM tests to be register allocator independent.Jakob Stoklund Olesen2011-03-3117-56/+83
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128680 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: APFloat can't perform arithmetic on PPC double doubles, don't ↵Benjamin Kramer2011-03-311-0/+9
| | | | | | | | even try. Thanks Eli! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128676 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test case for a malformed LDC/LDC2 instructions with PUDW = 0b0000, whichJohnny Chen2011-03-311-0/+11
| | | | | | | amounts to an UNDEFINED instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128668 91177308-0d34-0410-b5e6-96231b3b80d8
* Distribute (A + B) * C to (A * C) + (B * C) to make use of NEON multiplierEvan Cheng2011-03-311-1/+27
| | | | | | | | | | | | accumulator forwarding: vadd d3, d0, d1 vmul d3, d3, d2 => vmul d3, d0, d2 vmla d3, d1, d2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128665 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix single word and unsigned byte data transfer instruction encodings so thatJohnny Chen2011-03-311-0/+4
| | | | | | | | | Inst{4} = 0. rdar://problem/9213022 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128662 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Mips, Sparc, and XCore tests that were dependent on register allocation.Jakob Stoklund Olesen2011-03-316-49/+60
| | | | | | Add an extra run with -regalloc=basic to keep them honest. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128654 91177308-0d34-0410-b5e6-96231b3b80d8
* Added support for FP conditional move instructions and fixed bugs in ↵Akira Hatanaka2011-03-316-3/+349
| | | | | | handling of FP comparisons. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128650 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't completely eliminate identity copies that also modify super register ↵Jakob Stoklund Olesen2011-03-311-0/+1
| | | | | | | | | liveness. Turn them into noop KILL instructions instead. This lets the scavenger know when super-registers are killed and defined. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128645 91177308-0d34-0410-b5e6-96231b3b80d8
* Add BLXi to the instruction table for disassembly purpose.Johnny Chen2011-03-311-0/+3
| | | | | | | | | A8.6.23 BLX (immediate) rdar://problem/9212921 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128644 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark all uses as <undef> when joining a copy.Jakob Stoklund Olesen2011-03-311-1/+1
| | | | | | | | | | | | This way, shrinkToUses() will ignore the instruction that is about to be deleted, and we avoid leaving invalid live ranges that SplitKit doesn't like. Fix a misunderstanding in MachineVerifier about <def,undef> operands. The <undef> flag is valid on def operands where it has the same meaning as <undef> on a use operand. It only applies to sub-register defines which also read the full register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128642 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove stray empty test file.Daniel Dunbar2011-03-311-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128640 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r128632 again, until I figure out what break the testsBruno Cardoso Lopes2011-03-311-38/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128635 91177308-0d34-0410-b5e6-96231b3b80d8
* Add XCore intrinsics for initializing / starting / synchronizing threads.Richard Osborne2011-03-311-0/+67
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128633 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r128585 without generating a lib depedency cycle. An updated log:Bruno Cardoso Lopes2011-03-311-0/+38
| | | | | | | | | | | | | - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible. - Move all instructions which use am2offset without a pattern to use addrmode2. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128632 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Fix transform to use the swapped predicate.Benjamin Kramer2011-03-311-1/+1
| | | | | | Thanks Frits! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128628 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: fold fcmp (fneg x), (fneg y) -> fcmp x, yBenjamin Kramer2011-03-311-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128627 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: fold fcmp pred (fneg x), C -> fcmp swap(pred) x, -CBenjamin Kramer2011-03-311-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128626 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Shrink "fcmp (fpext x), C" to "fcmp x, C" if C can be ↵Benjamin Kramer2011-03-311-0/+23
| | | | | | | | losslessly converted to the type of x. Fixes PR9592. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128625 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: fold fcmp (fpext x), (fpext y) -> fcmp x, y.Benjamin Kramer2011-03-311-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128624 91177308-0d34-0410-b5e6-96231b3b80d8
* Will not compile without the spec!Duncan Sands2011-03-311-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128623 91177308-0d34-0410-b5e6-96231b3b80d8
* Testcase for r128619 (PR9571).Bill Wendling2011-03-311-0/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128620 91177308-0d34-0410-b5e6-96231b3b80d8
* Pick a conservative register class when creating a small live range for remat.Jakob Stoklund Olesen2011-03-311-0/+61
| | | | | | | | | | | | The rematerialized instruction may require a more constrained register class than the register being spilled. In the test case, the spilled register has been inflated to the DPR register class, but we are rematerializing a load of the ssub_0 sub-register which only exists for DPR_VFP2 registers. The register class is reinflated after spilling, so the conservative choice is only temporary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128610 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"Matt Beaumont-Gay2011-03-311-34/+0
| | | | | | This revision introduced a dependency cycle, as nlewycky mentioned by email. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128597 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't try to create zero-sized stack objects.Evan Cheng2011-03-301-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128586 91177308-0d34-0410-b5e6-96231b3b80d8
* - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT andBruno Cardoso Lopes2011-03-301-0/+34
| | | | | | | | | | | | | | | {STR,LDC}{2}_PRE. - Fixed the encoding in some places. - Some of those instructions were using am2offset and now use addrmode2. Codegen isn't affected, instructions which use SelectAddrMode2Offset were not touched. - Teach printAddrMode2Operand to check by the addressing mode which index mode to print. - This is a work in progress, more work to come. The idea is to change places which use am2offset to use addrmode2 instead, as to unify assembly parser. - Add testcases for assembly parser git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128585 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a ARM-specific SD node for VBSL so that forms with a constant first operandCameron Zwarich2011-03-301-0/+97
| | | | | | can be recognized. This fixes <rdar://problem/9183078>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128584 91177308-0d34-0410-b5e6-96231b3b80d8
* * The DSE code that tested for overlapping needed to take into account the factBill Wendling2011-03-301-0/+1
| | | | | | | | | | | | | that one of the numbers is signed while the other is unsigned. This could lead to a wrong result when the signed was promoted to an unsigned int. * Add the data layout line to the testcase so that it will test the appropriate thing. Patch by David Terei! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128577 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid turning a floating point division with a constant power of two into a ↵Benjamin Kramer2011-03-301-1/+1
| | | | | | | | | denormal multiplication. Some platforms may treat denormals as zero, on other platforms multiplication with a subnormal is slower than dividing by a normal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128555 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: If the divisor of an fdiv has an exact inverse, turn it into an ↵Benjamin Kramer2011-03-301-0/+25
| | | | | | | | fmul. Fixes PR9587. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128546 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test case for thumb stc2 instruction.Johnny Chen2011-03-301-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128517 91177308-0d34-0410-b5e6-96231b3b80d8
* Add intrinsics @llvm.arm.neon.vmulls and @llvm.arm.neon.vmullu.* back. FrontendsEvan Cheng2011-03-292-10/+101
| | | | | | | | | | | | | | | | was lowering them to sext / uxt + mul instructions. Unfortunately the optimization passes may hoist the extensions out of the loop and separate them. When that happens, the long multiplication instructions can be broken into several scalar instructions, causing significant performance issue. Note the vmla and vmls intrinsics are not added back. Frontend will codegen them as intrinsics vmull* + add / sub. Also note the isel optimizations for catching mul + sext / zext are not changed either. First part of rdar://8832507, rdar://9203134 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128502 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-08-03 23:11:43 +0000