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* Accept RIP-relative symbols with 'i' constraint, andDale Johannesen2010-07-061-0/+21
| | | | | | | | | print the (%rip) only if the 'a' modifier is present. PR 7528. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107727 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the rest of AVX SSE4.1 packed move with sign/zero extend instructionsBruno Cardoso Lopes2010-07-062-0/+95
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107723 91177308-0d34-0410-b5e6-96231b3b80d8
* Make test not hang waiting for input.Dale Johannesen2010-07-061-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107721 91177308-0d34-0410-b5e6-96231b3b80d8
* Add part of AVX SSE4.1 packed move with sign/zero extend instructionsBruno Cardoso Lopes2010-07-062-0/+97
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107720 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX vblendvpd, vblendvps and vpblendvb instructionsBruno Cardoso Lopes2010-07-062-0/+47
| | | | | | | Update VEX encoding to support those new instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107715 91177308-0d34-0410-b5e6-96231b3b80d8
* Be more forgiving when calculating alias interference for physreg coalescing.Jakob Stoklund Olesen2010-07-061-2/+2
| | | | | | | | | | | | It is OK for an alias live range to overlap if there is a copy to or from the physical register. CoalescerPair can work out if the copy is coalescable independently of the alias. This means that we can join with the actual destination interval instead of using the getOrigDstReg() hack. It is no longer necessary to merge clobber ranges into subregisters. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107695 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR7545 crash.Devang Patel2010-07-061-0/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107678 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversionRafael Espindola2010-07-061-1/+1
| | | | | | if profitable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107673 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove mistakenly added test.Eric Christopher2010-07-061-25/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107641 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix up -fstack-protector on linux to use the segmentEric Christopher2010-07-063-4/+57
| | | | | | | | | | registers. Split out testcases per architecture and os now. Patch from Nelson Elhage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107640 91177308-0d34-0410-b5e6-96231b3b80d8
* another v2f32 case, in this case showing poor codegen.Chris Lattner2010-07-051-1/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107614 91177308-0d34-0410-b5e6-96231b3b80d8
* fix test on non-x86 hosts.Chris Lattner2010-07-051-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107608 91177308-0d34-0410-b5e6-96231b3b80d8
* Just rip v2f32 support completely out of the X86 backend. InChris Lattner2010-07-041-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the example in the testcase, we now generate: _test1: ## @test1 movss 4(%esp), %xmm0 addss 8(%esp), %xmm0 movl 12(%esp), %eax movss %xmm0, (%eax) ret instead of: _test1: ## @test1 subl $20, %esp movl 24(%esp), %eax movq %mm0, (%esp) movq %mm0, 8(%esp) movss (%esp), %xmm0 addss 12(%esp), %xmm0 movss %xmm0, (%eax) addl $20, %esp ret v2f32 support did not work reliably because most of the X86 backend didn't know it was legal. It was apparently only added to support returning source-level v2f32 values in MMX registers in x86-32 mode. If ABI compatibility is important on this GCC-extended-vector type for some reason, then the frontend should generate IR that returns v2i32 instead of v2f32. However, we generally don't try very hard to be abi compatible on gcc extended vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107601 91177308-0d34-0410-b5e6-96231b3b80d8
* fix PR7518 - terrible codegen of <2 x float>, by only markingChris Lattner2010-07-041-0/+16
| | | | | | | | | v2f32 as legal in 32-bit mode. It is just as terrible there, but I just care about x86-64 and noone claims it is valuable in 64-bit mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107600 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX SSE4.1 blend, mpsadbw and vdpBruno Cardoso Lopes2010-07-032-0/+113
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107560 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX SSE4.1 binop (some forms of packed max,min,mul,pack,cmp) instructionsBruno Cardoso Lopes2010-07-032-0/+176
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107558 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX SSE4.1 Horizontal Minimum and Position instructionBruno Cardoso Lopes2010-07-032-0/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107552 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX SSE4.1 round instructionsBruno Cardoso Lopes2010-07-032-0/+64
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107549 91177308-0d34-0410-b5e6-96231b3b80d8
* - Add support for the rest of AVX SSE3 instructionsBruno Cardoso Lopes2010-07-022-0/+256
| | | | | | | | | - Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M represents a REX equivalent two byte leading opcode git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107523 91177308-0d34-0410-b5e6-96231b3b80d8
* - Two-address pass should not assume unfolding is always successful.Evan Cheng2010-07-021-0/+99
| | | | | | | | | | - X86 unfolding should check if the instructions being unfolded has memoperands. If there is no memoperands, then it must assume conservative alignment. If this would introduce an expensive sse unaligned load / store, then unfoldMemoryOperand etc. should not unfold the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107509 91177308-0d34-0410-b5e6-96231b3b80d8
* Propagate the AlignStack bit in InlineAsm's to the Dale Johannesen2010-07-025-4/+35
| | | | | | | | | | | | | | | | | | | | | PrologEpilog code, and use it to determine whether the asm forces stack alignment or not. gcc consistently does not do this for GCC-style asms; Apple gcc inconsistently sometimes does it for asm blocks. There is no convenient place to put a bit in either the SDNode or the MachineInstr form, so I've added an extra operand to each; unlovely, but it does allow for expansion for more bits, should we need it. PR 5125. Some existing testcases are affected. The operand lists of the SDNode and MachineInstr forms are indexed with awesome mnemonics, like "2"; I may fix this someday, but not now. I'm not making it any worse. If anyone is inspired I think you can find all the right places from this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107506 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix incorrect asm-printing of some NEON immediates. Fix weak testcase soBob Wilson2010-07-021-34/+20
| | | | | | | | that it checks the immediate values, not just the instructions opcodes. Radar 8110263. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107487 91177308-0d34-0410-b5e6-96231b3b80d8
* Prevent test from hanging waiting for input.Dale Johannesen2010-07-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107446 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM function alignments were off by a power of two. svn 83242 changedBob Wilson2010-07-011-0/+6
| | | | | | | | | | getFunctionAlignment and the corresponding use of that value in the ARM asm printer, but now we're using the standard asm printer. The result of this was that function alignments were dropped completely for Thumb functions. Radar 8143571. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107435 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the "linker_private_weak" linkage type. This will be used forBill Wendling2010-07-014-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | Objective-C metadata types which should be marked as "weak", but which the linker will remove upon final linkage. However, this linkage isn't specific to Objective-C. For example, the "objc_msgSend_fixup_alloc" symbol is defined like this: .globl l_objc_msgSend_fixup_alloc .weak_definition l_objc_msgSend_fixup_alloc .section __DATA, __objc_msgrefs, coalesced .align 3 l_objc_msgSend_fixup_alloc: .quad _objc_msgSend_fixup .quad L_OBJC_METH_VAR_NAME_1 This is different from the "linker_private" linkage type, because it can't have the metadata defined with ".weak_definition". Currently only supported on Darwin platforms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107433 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove context sensitivity concerns from interprocedural-basic-aa, andDan Gohman2010-07-012-7/+1739
| | | | | | | | make it more aggressive in cases where both pointers are known to live in the same function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107420 91177308-0d34-0410-b5e6-96231b3b80d8
* Debugging infomration is encoded in llvm IR using metadata. This is designedDevang Patel2010-07-011-0/+47
| | | | | | | | | | | such a way that debug info for symbols preserved even if symbols are optimized away by the optimizer. Add new special pass to remove debug info for such symbols. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107416 91177308-0d34-0410-b5e6-96231b3b80d8
* Move SSE3 Move patterns to a more appropriate sectionBruno Cardoso Lopes2010-07-012-0/+64
| | | | | | | Add AVX SSE3 packed horizontal and & sub instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107405 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX SSE3 packed addsub instructionsBruno Cardoso Lopes2010-07-012-0/+32
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107404 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily disable on-demand fast-isel.Dan Gohman2010-07-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107393 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach fast-isel to avoid loading a value from memory when it's alreadyDan Gohman2010-07-011-0/+23
| | | | | | | | available in a register. This is pretty primitive, but it reduces the number of instructions in common testcases by 4%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107380 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable on-demand fast-isel.Dan Gohman2010-07-011-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107377 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX SSE3 replicate and convert instructionsBruno Cardoso Lopes2010-07-012-0/+72
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107375 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach X86FastISel to fold constant offsets and scaled indices inDan Gohman2010-07-011-0/+19
| | | | | | | the same address. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107373 91177308-0d34-0410-b5e6-96231b3b80d8
* - Add AVX SSE2 Move doubleword and quadword instructions.Bruno Cardoso Lopes2010-07-012-0/+64
| | | | | | | | | | - Add encode bits for VEX_W - All 128-bit SSE 1 & SSE2 instructions that are described in the .td file now have a AVX encoded form already working. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107365 91177308-0d34-0410-b5e6-96231b3b80d8
* Test for the -filelist fix.Mikhail Glushenkov2010-07-011-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107363 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove all debug info related named mdnodes.Devang Patel2010-06-301-0/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107323 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX SSE2 mask creation and conditional store instructionsBruno Cardoso Lopes2010-06-302-0/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107306 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert the part of r107257 which introduced new logic for usingDan Gohman2010-06-301-3/+4
| | | | | | | | nsw and nuw flags from IR Instructions. On further consideration, this isn't valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107298 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX SSE2 packed integer extract/insert instructionsBruno Cardoso Lopes2010-06-302-0/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107293 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a testcase for scev-aa's new capability.Dan Gohman2010-06-301-3/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107258 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX SSE2 integer unpack instructionsBruno Cardoso Lopes2010-06-302-0/+128
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107246 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX SSE2 packed integer shuffle instructionsBruno Cardoso Lopes2010-06-302-0/+48
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107245 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX SSE2 pack with saturation integer instructionsBruno Cardoso Lopes2010-06-302-0/+48
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107241 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX SSE2 integer packed compare instructionsBruno Cardoso Lopes2010-06-302-0/+96
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107240 91177308-0d34-0410-b5e6-96231b3b80d8
* - Add AVX form of all SSE2 logical instructionsBruno Cardoso Lopes2010-06-302-0/+280
| | | | | | | - Add VEX encoding bits to x86 MRM0r-MRM7r git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107238 91177308-0d34-0410-b5e6-96231b3b80d8
* Add variables into a scope before constructing scope DIE otherwise variables ↵Devang Patel2010-06-301-0/+52
| | | | | | won't be included DIE tree. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107228 91177308-0d34-0410-b5e6-96231b3b80d8
* Add *several* AVX integer packed binop instructionsBruno Cardoso Lopes2010-06-292-0/+432
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107225 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ScalarEvolution's tripcount computation for chains of loopsDan Gohman2010-06-291-2/+64
| | | | | | | | where each loop's induction variable's start value is the exit value of a preceding loop. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107224 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX ld/st XCSR register.Bruno Cardoso Lopes2010-06-292-0/+24
| | | | | | | | Add VEX encoding bits for MRMXm x86 form git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107204 91177308-0d34-0410-b5e6-96231b3b80d8
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