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* Constants and Metadata share ValueList. This means they must be emitted ↵Devang Patel2009-08-041-0/+5
| | | | | | interleaved (using appropriate BLOCK_IDs) otherwise ValuePtrs index gets out of sync. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78033 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit sub r, #c instead of transforming it to add r, #-c if c fits in 8-bit. ↵Evan Cheng2009-08-041-1/+19
| | | | | | This is a bit of pre-mature optimization. 8-bit variant makes it likely it will be narrowed to a 16-bit instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78030 91177308-0d34-0410-b5e6-96231b3b80d8
* Add -disable-output. Thanks Bill!Dan Gohman2009-08-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78009 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new Constant::getIntegerValue helper function, and convert aDan Gohman2009-08-031-0/+84
| | | | | | | | few places in InstCombine to use it, to fix problems handling pointer types. This fixes the recent llvm-gcc bootstrap error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78005 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower CONCAT_VECTOR during legalization instead of matching it during isel.Bob Wilson2009-08-031-0/+36
| | | | | | | Add a testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77992 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Bug 4657: register scavenger asserts with subreg loweringJakob Stoklund Olesen2009-08-031-0/+29
| | | | | | | | | | | | | | | When LowerSubregsInstructionPass::LowerInsert eliminates an INSERT_SUBREG instriction because it is an identity copy, make sure that the same registers are alive before and after the elimination. When the super-register is marked <undef> this requires inserting an IMPLICIT_DEF instruction to make sure the super register is live. Fix a related bug where a kill flag on the inserted sub-register was not transferred properly. Finally, clear the undef flag in MachineInstr::addRegisterKilled. Undef implies dead and kill implies live, so they cant both be valid. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77989 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a coaelescer bug. If a copy val# is extended to eliminate a ↵Evan Cheng2009-08-031-0/+46
| | | | | | non-trivially coalesced copy, and the copy kills its source register. Trim the source register's live range to the last use if possible. This fixes up kill marker to make the scavenger happy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77967 91177308-0d34-0410-b5e6-96231b3b80d8
* Unbreak Win64 CC. Step one: honour register save area, fix some alignment ↵Anton Korobeynikov2009-08-032-4/+4
| | | | | | and provide a different set of call-clobberred registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77962 91177308-0d34-0410-b5e6-96231b3b80d8
* Use movd instead of movqRafael Espindola2009-08-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77956 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass target triple string in to TargetMachine constructor.Daniel Dunbar2009-08-033-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is not just a matter of passing in the target triple from the module; currently backends are making decisions based on the build and host architecture. The goal is to migrate to making these decisions based off of the triple (in conjunction with the feature string). Thus most clients pass in the target triple, or the host triple if that is empty. This has one important change in the way behavior of the JIT and llc. For the JIT, it was previously selecting the Target based on the host (naturally), but it was setting the target machine features based on the triple from the module. Now it is setting the target machine features based on the triple of the host. For LLC, -march was previously only used to select the target, the target machine features were initialized from the module's triple (which may have been empty). Now the target triple is taken from the module, or the host's triple is used if that is empty. Then the triple is adjusted to match -march. The take away is that -march for llc is now used in conjunction with the host triple to initialize the subtarget. If users want more deterministic behavior from llc, they should use -mtriple, or set the triple in the input module. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77946 91177308-0d34-0410-b5e6-96231b3b80d8
* Use movq to move 64 bits in and out of mmx registers.Rafael Espindola2009-08-032-1/+11
| | | | | | | | Fixes PR4669 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77940 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the i12 variant of load / store opcodes if offset is zero. Now we pass ↵Evan Cheng2009-08-031-0/+85
| | | | | | all of multisource as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77939 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand LDA testcases.Andreas Bolka2009-08-022-11/+62
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77926 91177308-0d34-0410-b5e6-96231b3b80d8
* Add extra SEXT pattern.Richard Osborne2009-08-021-0/+32
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77920 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unneeded intrinsics from Blackfin backend.Jakob Stoklund Olesen2009-08-021-13/+0
| | | | | | | | | | __builtin_bfin_ones does the same as ctpop, so it can be implemented in the front-end. __builtin_bfin_loadbytes loads from an unaligned pointer with the disalignexcpt instruction. It does the same as loading from a pointer with the low bits masked. It is better if the front-end creates a masked load. We can always instruction select the masked to disalignexcpt+load. We keep csync/ssync/idle. These intrinsics represent instructions that need workarounds for some silicon revisions. We may even want to convert inline assembler to intrinsics to enable the workarounds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77917 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix issue in regscavenger when scavenging a callee-saved register that has ↵Jakob Stoklund Olesen2009-08-021-3/+3
| | | | | | not been spilled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77912 91177308-0d34-0410-b5e6-96231b3b80d8
* Never add a kill flag to a constrained physical register in a two-addr ↵Jakob Stoklund Olesen2009-08-022-6/+0
| | | | | | instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77906 91177308-0d34-0410-b5e6-96231b3b80d8
* Scavenger asserts.Jakob Stoklund Olesen2009-08-021-3/+0
| | | | | | | Allow imp-def and imp-use of anything in the scavenger asserts, just like the machine code verifier. Allow redefinition of a sub-register of a live register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77904 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some basic blackfin intrinsics.Jakob Stoklund Olesen2009-08-022-0/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77903 91177308-0d34-0410-b5e6-96231b3b80d8
* Inline assembly support for Blackfin.Jakob Stoklund Olesen2009-08-021-0/+38
| | | | | | We use the same constraints as GCC, including those that are slightly insane for inline assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77899 91177308-0d34-0410-b5e6-96231b3b80d8
* Analog Devices Blackfin back-end.Jakob Stoklund Olesen2009-08-0247-0/+1238
| | | | | | | | | | | | | | Generate code for the Blackfin family of DSPs from Analog Devices: http://www.analog.com/en/embedded-processing-dsp/blackfin/processors/index.html We aim to be compatible with the exsisting GNU toolchain found at: http://blackfin.uclinux.org/gf/project/toolchain The back-end is experimental. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77897 91177308-0d34-0410-b5e6-96231b3b80d8
* Test both darwin and linux.Evan Cheng2009-08-021-5/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77852 91177308-0d34-0410-b5e6-96231b3b80d8
* switch to filecheck formatChris Lattner2009-08-021-12/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77841 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a problem Eli noticed where we would compile the attached ptrtointChris Lattner2009-08-011-0/+8
| | | | | | | | | | | | | | | | | to: .quad X even on a 32-bit system, where X is not 64-bits. There isn't much that we can do here, so we just print: .quad ((X) & 4294967295) instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77818 91177308-0d34-0410-b5e6-96231b3b80d8
* Add nounwind to this test.Dan Gohman2009-08-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77792 91177308-0d34-0410-b5e6-96231b3b80d8
* Hack to make this test work on platforms which aren't Macs. Fixing this Eli Friedman2009-08-011-1/+1
| | | | | | | | | | | | myself because I'm getting tired of seeing the red buildbots, which have been red since 5:30PM PDT last night. Proposed supplement to developer policy: committers should make sure to be around to watch for buildbot failures after committing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77785 91177308-0d34-0410-b5e6-96231b3b80d8
* Workaround a couple of Darwin assembler bugs.Evan Cheng2009-08-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77781 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid a problem with ulimit on Solaris & friends, patch by Edward O'Callaghan!Daniel Dunbar2009-08-011-4/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77767 91177308-0d34-0410-b5e6-96231b3b80d8
* Split t2MOVCCs since some assemblers do not recognize mov shifted register ↵Evan Cheng2009-08-011-0/+35
| | | | | | alias with predicate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77764 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-mc: More quoted identifier support.Daniel Dunbar2009-08-011-0/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77761 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the sameEvan Cheng2009-08-012-1/+21
| | | | | | | | | | instructions for calls since BL and BLX are always 32-bit long and BX is always 16-bit long. Also, we should be using BLX to call external function stubs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77756 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-mc: Add -triple, and fix some typosDaniel Dunbar2009-07-312-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77750 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-mc: Fix .s output to quote section & symbol names when necessary.Daniel Dunbar2009-07-312-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77749 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-mc: A few more parsing / match tweaks.Daniel Dunbar2009-07-311-0/+27
| | | | | | | | | | | | | | | - Operands which are just a label should be parsed as immediates, not memory operands (from the assembler perspective). - Match a few more flavors of immediates. - Distinguish match functions for memory operands which don't take a segment register. - We match the .s for "hello world" now! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77745 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify operand padding by keying off tabs in the asm stream. IfDavid Greene2009-07-315-13/+13
| | | | | | | | | | | | | padding is disabled, tabs get replaced by spaces except in the case of the first operand, where the tab is output to line up the operands after the mnemonics. Add some better comments and eliminate redundant code. Fix some testcases to not assume tabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77740 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-mc: Support quoted identifiers.Daniel Dunbar2009-07-311-0/+26
| | | | | | | | | | - Uses MCAsmToken::getIdentifier which returns the (sub)string representing the meaningfull contents a string or identifier token. - Directives aren't done yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77739 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-mc/X86: Sketch match functions for immediates and memory operands.Daniel Dunbar2009-07-311-2/+14
| | | | | | | | Also, change scale value to always be 1 when unspecified to machine MachineInst encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77728 91177308-0d34-0410-b5e6-96231b3b80d8
* PR4662: Fix a crash introduced by the recent LLVMContext changes.Eli Friedman2009-07-311-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77716 91177308-0d34-0410-b5e6-96231b3b80d8
* switch off of 'Section' onto MCSection. We're not properly usingChris Lattner2009-07-311-2/+1
| | | | | | | | MCSection subclasses yet, but this is a step in the right direction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77708 91177308-0d34-0410-b5e6-96231b3b80d8
* Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .alignEvan Cheng2009-07-311-0/+1
| | | | | | | | | to ensure the instruction that follows a TBB (when the number of table entries is odd) is 2-byte aligned. Patch by Sandeep Patel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77705 91177308-0d34-0410-b5e6-96231b3b80d8
* fix PR4650: we only track sizes for certain objects, so only put somethingChris Lattner2009-07-311-0/+17
| | | | | | | | | into the mergable section if it is one of our special cases. This could obviously be improved, but this is the minimal fix and restores us to the previous behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77679 91177308-0d34-0410-b5e6-96231b3b80d8
* Add this test back, the check pattern was too strict.Daniel Dunbar2009-07-311-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77662 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove this test while I figure out why it is failing.Daniel Dunbar2009-07-311-5/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77659 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-mc: Match a few X86 instructions.Daniel Dunbar2009-07-312-1/+6
| | | | | | | | | | | | - This is "experimental" code, I am feeling my way around and working out the best way to do things (and learning tblgen in the process). Comments welcome, but keep in mind this stuff will change radically. - This is enough to match "subb" and friends, but not much else. The next step is to automatically generate the matchers for individual operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77657 91177308-0d34-0410-b5e6-96231b3b80d8
* When fp is not eliminated, instructions with T2_i12 modes will be changed to ↵Evan Cheng2009-07-301-0/+193
| | | | | | T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77642 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not use abbrev while writing NamedMDNode name.Devang Patel2009-07-301-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77637 91177308-0d34-0410-b5e6-96231b3b80d8
* Darwin assembler now recognizes "orn", so remove workaround.David Goodwin2009-07-302-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77627 91177308-0d34-0410-b5e6-96231b3b80d8
* Darwin assembler now supports "rrx", so remove workaround.David Goodwin2009-07-301-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77625 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup and include code selection for some frame index cases.David Goodwin2009-07-301-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77622 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize some common usage patterns of atomic built-ins ↵Evan Cheng2009-07-302-1/+221
| | | | | | | | | | | | | __sync_add_and_fetch() and __sync_sub_and_fetch. When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix. This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection. Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77582 91177308-0d34-0410-b5e6-96231b3b80d8
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