aboutsummaryrefslogtreecommitdiffstats
path: root/test
Commit message (Collapse)AuthorAgeFilesLines
...
* instcombine: Add more test cases for __strcpy_chk simplificationMeador Inge2012-09-273-13/+109
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164799 91177308-0d34-0410-b5e6-96231b3b80d8
* instcombine: Add more test cases for __memmove_chk simplificationMeador Inge2012-09-272-0/+84
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164798 91177308-0d34-0410-b5e6-96231b3b80d8
* instcombine: Add more test cases for __memcpy_chk simplificationMeador Inge2012-09-272-0/+84
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164797 91177308-0d34-0410-b5e6-96231b3b80d8
* instcombine: Add more test cases for __memset_chk simplificationMeador Inge2012-09-273-18/+81
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164796 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable the new coalescer algorithm by default.Jakob Stoklund Olesen2012-09-271-1/+0
| | | | | | | The new coalescer is better at merging values into unused vector lanes, improving NEON code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164794 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS DSP: ABSQ_S.PH instruction sub-class.Akira Hatanaka2012-09-272-0/+215
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164787 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS DSP: SHLL.QB instruction sub-class.Akira Hatanaka2012-09-272-0/+252
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164786 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a integer overflow in SimplifyCFG's look up table formation logic.Benjamin Kramer2012-09-271-0/+38
| | | | | | | | If the width is very large it gets truncated from uint64_t to uint32_t when passed to TD->fitsInLegalInteger. The truncated value can fit in a register. This manifested in massive memory usage or crashes (PR13946). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164784 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid dereferencing a NULL pointer.Jakob Stoklund Olesen2012-09-271-0/+35
| | | | | | Fixes PR13943. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164778 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. ↵Sylvestre Ledru2012-09-274-6/+6
| | | | | | See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo 'iff' => 'if'Sylvestre Ledru2012-09-274-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164767 91177308-0d34-0410-b5e6-96231b3b80d8
* Prefer shuffles to selects. Backends love shuffles!Nick Lewycky2012-09-272-1/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164763 91177308-0d34-0410-b5e6-96231b3b80d8
* [arm-fast-isel] Add support for ELF PIC.Jush Lu2012-09-271-0/+18
| | | | | | | | This is a preliminary step towards ELF support; currently ARMFastISel hasn't been used for ELF object files yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164759 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for r164755 and 164756.Akira Hatanaka2012-09-272-0/+294
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164757 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS DSP: ADDU.QB instruction sub-class.Akira Hatanaka2012-09-272-0/+309
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164754 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos ↵Akira Hatanaka2012-09-271-0/+10
| | | | | | Field instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164751 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS DSP: all the remaining instructions which read or write accumulators.Akira Hatanaka2012-09-272-0/+348
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164750 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS DSP: add support for extract-word instructions.Akira Hatanaka2012-09-271-0/+110
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164749 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS DSP: add vector load/store patterns.Akira Hatanaka2012-09-271-0/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164744 91177308-0d34-0410-b5e6-96231b3b80d8
* X86_32: Large Symbol+Offset relocations.Jim Grosbach2012-09-261-0/+36
| | | | | | | | | | If the offset is more than 24-bits, it won't fit in a scattered relocation offset field, so we fall back to using a non-scattered relocation. rdar://12358909 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164724 91177308-0d34-0410-b5e6-96231b3b80d8
* Now that invoke of an intrinsic is possible (for the llvm.do.nothing intrinsic)Duncan Sands2012-09-261-0/+13
| | | | | | | | teach the callgraph logic to not create callgraph edges to intrinsics for invoke instructions; it already skips this for call instructions. Fixes PR13903. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164707 91177308-0d34-0410-b5e6-96231b3b80d8
* Address Duncan's comments on r164684:Hans Wennborg2012-09-261-2/+2
| | | | | | | | - Put statistics in alphabetical order - Don't use getZextValue when building TableInt, just use APInts - Introduce Create{Z,S}ExtOrTrunc in IRBuilder. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164696 91177308-0d34-0410-b5e6-96231b3b80d8
* When rewriting the pointer operand to a load or store which hasChandler Carruth2012-09-261-0/+18
| | | | | | | alignment guarantees attached, re-compute the alignment so that we consider offsets which impact alignment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164690 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach all of the loads, stores, memsets and memcpys created by theChandler Carruth2012-09-262-15/+46
| | | | | | | | | | | | | rewriter in SROA to carry a proper alignment. This involves interrogating various sources of alignment, etc. This is a more complete and principled fix to PR13920 as well as related bugs pointed out by Eli in review and by inspection in the area. Also by inspection fix the integer and vector promotion paths to create aligned loads and stores. I still need to work up test cases for these... Sorry for the delay, they were found purely by inspection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164689 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM/atomicrmw_minmax.ll: Fix RUN line.NAKAMURA Takumi2012-09-261-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164687 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix tests that didn't test anything.Benjamin Kramer2012-09-263-4/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164686 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ordering of operands on lowering of atomicrmw min/max nodes on ARM.James Molloy2012-09-261-0/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164685 91177308-0d34-0410-b5e6-96231b3b80d8
* SimplifyCFG: Make the switch-to-lookup table transformation store theHans Wennborg2012-09-261-14/+73
| | | | | | | | | | | | | | | | tables in bitmaps when they fit in a target-legal register. This saves some space, and it also allows for building tables that would otherwise be deemed too sparse. One interesting case that this hits is example 7 from http://blog.regehr.org/archives/320. We currently generate good code for this when lowering the switch to the selection DAG: we build a bitmask to decide whether to jump to one block or the other. My patch will result in the same bitmask, but it removes the need for the jump, as the return value can just be retrieved from the mask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164684 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm/test/CodeGen/X86/mulx*.ll: Fix copypasto.NAKAMURA Takumi2012-09-262-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164681 91177308-0d34-0410-b5e6-96231b3b80d8
* Add SARX/SHRX/SHLX code generation supportMichael Liao2012-09-263-2/+180
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164675 91177308-0d34-0410-b5e6-96231b3b80d8
* Add RORX code generation supportMichael Liao2012-09-264-5/+59
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164674 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MULX code generation supportMichael Liao2012-09-262-0/+44
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164673 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the 'lint' sanity checking pass to detect simple buffer overflows.Duncan Sands2012-09-261-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164671 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert the business end of r164636 and try again. I'll come in again. ;]Chandler Carruth2012-09-261-13/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This should really, really fix PR13916. For real this time. The underlying bug is... a bit more subtle than I had imagined. The setup is a code pattern that leads to an @llvm.memcpy call with two equal pointers to an alloca in the source and dest. Now, not any pattern will do. The alloca needs to be formed just so, and both pointers should be wrapped in different bitcasts etc. When this precise pattern hits, a funny sequence of events transpires. First, we correctly detect the potential for overlap, and correctly optimize the memcpy. The first time. However, we do simplify the set of users of the alloca, and that causes us to run the alloca back through the SROA pass in case there are knock-on simplifications. At this point, a curious thing has happened. If we happen to have an i8 alloca, we have direct i8 pointer values. So we don't bother creating a cast, we rewrite the arguments to the memcpy to dircetly refer to the alloca. Now, in an unrelated area of the pass, we have clever logic which ensures that when visiting each User of a particular pointer derived from an alloca, we only visit that User once, and directly inspect all of its operands which refer to that particular pointer value. However, the mechanism used to detect memcpy's with the potential to overlap relied upon getting visited once per *Use*, not once per *User*. This is always true *unless* the same exact value is both source and dest. It turns out that almost nothing actually produces that pattern though. We can hand craft test cases that more directly test this behavior of course, and those are included. Also, note that there is a significant missed optimization here -- we prove in many cases that there is a non-volatile memcpy call with identical source and dest addresses. We shouldn't prevent splitting the alloca in that case, and in fact we should just remove such memcpy calls eagerly. I'll address that in a subsequent commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164669 91177308-0d34-0410-b5e6-96231b3b80d8
* Generate an error message instead of asserting or segfaulting when we have aBill Wendling2012-09-261-0/+11
| | | | | | | | | scalar-to-vector conversion that we cannot handle. For instance, when an invalid constraint is used in an inline asm statement. <rdar://problem/12284092> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164662 91177308-0d34-0410-b5e6-96231b3b80d8
* Generate an error message instead of asserting or segfaulting when we have aBill Wendling2012-09-261-0/+11
| | | | | | | | | scalar-to-vector conversion that we cannot handle. For instance, when an invalid constraint is used in an inline asm statement. <rdar://problem/12284092> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164657 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't drop the alignment on a memcpy intrinsic when producing a store. This isNick Lewycky2012-09-251-0/+16
| | | | | | | | | only a missed optimization opportunity if the store is over-aligned, but a miscompile if the store's new type has a higher natural alignment than the memcpy did. Fixes PR13920! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164641 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't try to promote the same alloca twice. Fixes PR13916!Nick Lewycky2012-09-251-0/+22
| | | | | | | | | Chandler, it's not obvious that it's okay that this alloca gets into the list twice to begin with. Please review and see whether this is the fix you really want, but I wanted to get a fix checked in quickly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164634 91177308-0d34-0410-b5e6-96231b3b80d8
* Make this test check the transforms it's actually doing. Also add a test that itNick Lewycky2012-09-251-3/+17
| | | | | | | doesn't transform the trivially unsafe case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164617 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing i64 max/min/umax/umin on 32-bit targetMichael Liao2012-09-252-1/+51
| | | | | | | | - Turn on atomic6432.ll and add specific test case as well git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164616 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Darwin BL/BLX relocations to out-of-range symbols.Jim Grosbach2012-09-251-0/+43
| | | | | | | | | | | When a BL/BLX references a symbol in the same translation unit that is out of range, use an external relocation. The linker will use this to generate a branch island rather than a direct reference, allowing the relocation to resolve correctly. rdar://12359919 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164615 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a case where SROA did not correctly detect dead PHI or selects dueChandler Carruth2012-09-251-0/+45
| | | | | | | | to chains or cycles between PHIs and/or selects. Also add a couple of really nice test cases reduced from Kostya's reports in PR13905 and PR13906. Both are fixed by this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164596 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the way the lint sanity checking pass detects misaligned memory accesses.Duncan Sands2012-09-251-2/+6
| | | | | | | | | | | | | | | | Previously it was only be able to detect problems if the pointer was a numerical value (eg inttoptr i32 1 to i32*), but not if it was an alloca or globa. The reason was the use of ComputeMaskedBits: imagine you have "alloca i8, align 2", and ask ComputeMaskedBits what it knows about the bits of the alloca pointer. It can tell you that the bottom bit is known zero (due to align 2) but it can't tell you that bit 1 is known one. That's because the address could be an even multiple of 2 rather than an odd multiple, eg it might be a multiple of 4. Thus trying to use KnownOne is ineffective in the case of an alloca as it will never have any bits set. Instead look explicitly for constant offsets from allocas and globals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164595 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an illegal tailcall opt where the callee returns a double via xmm while ↵Evan Cheng2012-09-251-3/+26
| | | | | | caller returns x86_fp80 via st0. rdar://12229511 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164588 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't forget that strcpy and friends return a pointer to the destination, soNick Lewycky2012-09-251-0/+10
| | | | | | | it's not a dead store if that pointer is used. Whoops! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164583 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: 'add Rd, pc, #imm' is an alias for 'adr Rd, #imm'.Jim Grosbach2012-09-251-0/+4
| | | | | | rdar://9795790 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164577 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark jump tables in code sections with DataRegion directives.Jim Grosbach2012-09-241-0/+12
| | | | | | | | | Even out-of-line jump tables can be in the code section, so mark them as data-regions for those targets which support the directives. rdar://12362871&12362974 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164571 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach DSE that strcpy, strncpy, strcat and strncat are all stores which may beNick Lewycky2012-09-241-0/+46
| | | | | | | dead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164561 91177308-0d34-0410-b5e6-96231b3b80d8
* Specify MachinePointerInfo as refering to the argument value and offset of theRoman Divacky2012-09-241-0/+27
| | | | | | | | store when handling byval arguments. Thus preventing reordering of the store with load with post-RA scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164553 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing : in CHECK line.Richard Osborne2012-09-241-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164540 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-03-24 13:06:39 +0000