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* Revert r165661, "Patch by Shuxin Yang <shuxin.llvm@gmail.com>."NAKAMURA Takumi2012-10-111-16/+0
| | | | | | It broke stage2 clang and test-suite/MultiSource/Benchmarks/mediabench/g721/g721encode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165692 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't crash if a .ll file contains a forward-reference that looks like a globalNick Lewycky2012-10-111-0/+4
| | | | | | | | | | value but later turns out to be a function. Unfortunately, we can't fold tests into a single file because we only get one error out of llvm-as. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165680 91177308-0d34-0410-b5e6-96231b3b80d8
* Add isel patterns for v2f32 / v4f32 neon.vbsl intrinsics. rdar://12471808Evan Cheng2012-10-101-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165673 91177308-0d34-0410-b5e6-96231b3b80d8
* Add -mattr=+altivec and remove XFAIL.Bill Schmidt2012-10-101-3/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165666 91177308-0d34-0410-b5e6-96231b3b80d8
* XFAIL for all targets pending investigationBill Schmidt2012-10-101-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165664 91177308-0d34-0410-b5e6-96231b3b80d8
* Patch by Shuxin Yang <shuxin.llvm@gmail.com>.Nadav Rotem2012-10-101-0/+16
| | | | | | | | | | | | | | | | | | | | | Original message: The attached is the fix to radar://11663049. The optimization can be outlined by following rules: (select (x != c), e, c) -> select (x != c), e, x), (select (x == c), c, e) -> select (x == c), x, e) where the <c> is an integer constant. The reason for this change is that : on x86, conditional-move-from-constant needs two instructions; however, conditional-move-from-register need only one instruction. While the LowerSELECT() sounds to be the most convenient place for this optimization, it turns out to be a bad place. The reason is that by replacing the constant <c> with a symbolic value, it obscure some instruction-combining opportunities which would otherwise be very easy to spot. For that reason, I have to postpone the change to last instruction-combining phase. The change passes the test of "make check-all -C <build-root/test" and "make -C project/test-suite/SingleSource". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165661 91177308-0d34-0410-b5e6-96231b3b80d8
* When generating spill and reload code for vector registers on PowerPC,Bill Schmidt2012-10-101-0/+19
| | | | | | | | | | | | | the compiler makes use of GPR0. However, there are two flavors of GPR0 defined by the target: the 32-bit GPR0 (R0) and the 64-bit GPR0 (X0). The spill/reload code makes use of R0 regardless of whether we are generating 32- or 64-bit code. This patch corrects the problem in the obvious manner, using X0 and ADDI8 for 64-bit and R0 and ADDI for 32-bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165658 91177308-0d34-0410-b5e6-96231b3b80d8
* The PowerPC VRSAVE register has been somewhat of an odd beast sinceBill Schmidt2012-10-101-0/+15
| | | | | | | | | | | | | | | | | | | the Altivec extensions were introduced. Its use is optional, and allows the compiler to communicate to the operating system which vector registers should be saved and restored during a context switch. In practice, this information is ignored by the various operating systems using the SVR4 ABI; the kernel saves and restores the entire register state. Setting the VRSAVE register is no longer performed by the AIX XL compilers, the IBM i compilers, or by GCC on Power Linux systems. It seems best to avoid this logic within LLVM as well. This patch avoids generating code to update and restore VRSAVE for the PowerPC SVR4 ABIs (32- and 64-bit). The code remains in place for the Darwin ABI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165656 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the testcase from pr13254 (the old scalarreply pass handles this wrong;Duncan Sands2012-10-101-0/+16
| | | | | | | the new sroa pass handles it right). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165644 91177308-0d34-0410-b5e6-96231b3b80d8
* Specify CPU model to avoid breaking ATOM buildsMichael Liao2012-10-102-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165638 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for FP_ROUND from v2f64 to v2f32Michael Liao2012-10-102-14/+98
| | | | | | | | | | | | - Due to the current matching vector elements constraints in ISD::FP_ROUND, rounding from v2f64 to v4f32 (after legalization from v2f32) is scalarized. Add a customized v2f32 widening to convert it into a target-specific X86ISD::VFPROUND to work around this constraints. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165631 91177308-0d34-0410-b5e6-96231b3b80d8
* [CMake] check-all: Don't include check-llvm into check-all without ↵NAKAMURA Takumi2012-10-101-0/+5
| | | | | | | | LLVM_BUILD_TOOLS. FIXME: Would you like to run llvm/unittests w/o LLVM_BUILD_TESTS regardless of LLVM_BUILD_TOOLS? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165619 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for LDRB instruction:Stepan Dyatkovskiy2012-10-101-0/+23
| | | | | | | | | | | | | | | | | | | | | SDNode for LDRB_POST_IMM is invalid: number of registers added to SDNode fewer that described in .td. 7 ops is needed, but SDNode with only 6 is created. In more details: In ARMInstrInfo.td, in multiclass AI2_ldridx, in definition _POST_IMM, offset operand is defined as am2offset_imm. am2offset_imm is complex parameter type, and actually it consists from dummy register and imm itself. As I understood trick with dummy reg was made for AsmParser. In ARMISelLowering.cpp, this dummy register was not added to SDNode, and it cause crash in Peephole Optimizer pass. The problem fixed by setting up additional dummy reg when emitting LDRB_POST_IMM instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165617 91177308-0d34-0410-b5e6-96231b3b80d8
* Issue description:Stepan Dyatkovskiy2012-10-101-0/+19
| | | | | | | | | | | | | | | | | | | | | | SchedulerDAGInstrs::buildSchedGraph ignores dependencies between FixedStack objects and byval parameters. So loading byval parameters from stack may be inserted *before* it will be stored, since these operations are treated as independent. Fix: Currently ARMTargetLowering::LowerFormalArguments saves byval registers with FixedStack MachinePointerInfo. To fix the problem we need to store byval registers with MachinePointerInfo referenced to first the "byval" parameter. Also commit adds two new fields to the InputArg structure: Function's argument index and InputArg's part offset in bytes relative to the start position of Function's argument. E.g.: If function's argument is 128 bit width and it was splitted onto 32 bit regs, then we got 4 InputArg structs with same arg index, but different offset values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165616 91177308-0d34-0410-b5e6-96231b3b80d8
* Test case for r165480.Craig Topper2012-10-101-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165594 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement MipsTargetLowering::CanLowerReturn.Akira Hatanaka2012-10-101-0/+244
| | | | | | | Patch by Sasa Stankovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165585 91177308-0d34-0410-b5e6-96231b3b80d8
* When expanding atomic load arith instructions, do not lose target flags. ↵Evan Cheng2012-10-091-42/+58
| | | | | | rdar://12453106 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165568 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial assembler implementation of Mips load address macroJack Carter2012-10-091-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides initial implementation of load address macro instruction for Mips. We have implemented two kinds of expansions with their variations depending on the size of immediate operand: 1) load address with immediate value directly: * la d,j => addiu d,$zero,j (for -32768 <= j <= 65535) * la d,j => lui d,hi16(j) ori d,d,lo16(j) (for any other 32 bit value of j) 2) load load address with register offset value * la d,j(s) => addiu d,s,j (for -32768 <= j <= 65535) * la d,j(s) => lui d,hi16(j) (for any other 32 bit value of j) ori d,d,lo16(j) addu d,d,s This patch does not cover the case when the address is loaded from the value of the label or function. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165561 91177308-0d34-0410-b5e6-96231b3b80d8
* Inline the checks for mutually exclusive attributes since they're used in ↵Bill Wendling2012-10-091-1/+1
| | | | | | only one module. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165539 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable response files in all tools. Patch by Liu, Yaxun (Sam). I have simplifiedRafael Espindola2012-10-091-0/+9
| | | | | | the test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165535 91177308-0d34-0410-b5e6-96231b3b80d8
* New EarlyCSE tests for CSE-ing across commutativity.Michael Ilseman2012-10-091-0/+66
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165510 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR14016.Alexey Samsonov2012-10-091-0/+64
| | | | | | | | | | | DeadArgumentElimination pass can replace one LLVM function with another, invalidating a pointer stored in debug info metadata entry for this function. To fix this, we collect debug info descriptors for functions before running a DeadArgumentElimination pass and "patch" pointers in metadata nodes if we replace a function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165490 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r117093, "test/Makefile: Force lit -j1 on Cygwin."NAKAMURA Takumi2012-10-091-5/+0
| | | | | | lit -jN works on cygwin in most cases, but still sometimes I can see stalls with iterative run on the buildbot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165482 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR14034, an infloop / heap corruption / crash bug in the new SROA.Chandler Carruth2012-10-091-0/+20
| | | | | | | Thanks to Benjamin for the raw test case. This one took about 50 times longer to reduce than to fix. =/ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165476 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't crash on extra evil irreducible control flow.Jakob Stoklund Olesen2012-10-081-0/+75
| | | | | | | | | | | | | | When the CFG contains a loop with multiple entry blocks, the traces computed by MachineTraceMetrics don't always have the same nice properties. Loop back-edges are normally excluded from traces, but MachineLoopInfo doesn't recognize loops with multiple entry blocks, so those back-edges may be included. Avoid asserting when that happens by adding an isEarlierInSameTrace() function that accurately determines if a dominating block is part of the same trace AND is above the currrent block in the trace. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165434 91177308-0d34-0410-b5e6-96231b3b80d8
* PR12716: PPC crashes on vector compareAdhemerval Zanella2012-10-081-0/+191
| | | | | | | | | | | | | | | | | | | | Vector compare using altivec 'vcmpxxx' instructions have as third argument a vector register instead of CR one, different from integer and float-point compares. This leads to a failure in code generation, where 'SelectSETCC' expects a DAG with a CR register and gets vector register instead. This patch changes the behavior by just returning a DAG with the vector compare instruction based on the type. The patch also adds a testcase for all vector types llvm defines. It also included a fix on signed 5-bits predicates printing, where signed values were not handled correctly as signed (char are unsigned by default for PowerPC). This generates 'vspltisw' (vector splat) instruction with SIM out of range. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165419 91177308-0d34-0410-b5e6-96231b3b80d8
* Add floating-point to and from integer conversionAdhemerval Zanella2012-10-081-0/+57
| | | | | | | | This patch add altivec support for v4i32 to v4f32 and for v4f32 to v4i32 vector rounding conversion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165409 91177308-0d34-0410-b5e6-96231b3b80d8
* Move TargetData to DataLayout.Micah Villmow2012-10-084-11/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165403 91177308-0d34-0410-b5e6-96231b3b80d8
* Some regression tests which are testing the old jit and are exercising ↵James Molloy2012-10-083-0/+3
| | | | | | | | | | functionality which is both known to be broken and not expected to be fixed in the old jit. To remove these from the regression test output, I've marked them XFAIL (for lit tests) and ifdef'd them out (unit tests). These modifications remove the last long-standing regression test failures from the buildbots (though updating the triple to reflect new ubuntu configuration has temporarily caused some new failures). Tested on x86-64 and ARM Linux. Patch by David Tweed! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165390 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: fcmov doesn't handle all possible EFLAGS, fall back to a branch for the ↵Benjamin Kramer2012-10-071-0/+451
| | | | | | | | | others. Otherwise it will try to use SSE patterns and fail horribly if sse is disabled. Fixes PR14035. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165377 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding support for instructions mfc0, mfc2, mtc0, mtc2Jack Carter2012-10-061-0/+16
| | | | | | | | | move from and to coprocessors 0 and 2. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165351 91177308-0d34-0410-b5e6-96231b3b80d8
* Patch for integer multiply, signed/unsigned, long/long long.Reed Kotler2012-10-053-0/+59
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165322 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable llvm/test/ExecutionEngine/MCJIT also for cygwin.NAKAMURA Takumi2012-10-052-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165313 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert to unix line endings.Rafael Espindola2012-10-051-68/+68
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165308 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure to generate the right kind of MDNode for enum forward declarations.Eli Friedman2012-10-051-9/+7
| | | | | | | | PR14029, LLVM part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165288 91177308-0d34-0410-b5e6-96231b3b80d8
* Follow up to r165072. Try a different approach: only move the load when it's ↵Evan Cheng2012-10-051-0/+36
| | | | | | going to be folded into the call. rdar://12437604 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165287 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the new SROA a new trick. Now we zap any memcpy or memmoves whichChandler Carruth2012-10-051-4/+2
| | | | | | | | | | | | are in fact identity operations. We detect these and kill their partitions so that even splitting is unaffected by them. This is particularly important because Clang relies on emitting identity memcpy operations for struct copies, and these fold away to constants very often after inlining. Fixes the last big performance FIXME I have on my plate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165285 91177308-0d34-0410-b5e6-96231b3b80d8
* When merging connsecutive stores, use vectors to store the constant zero.Nadav Rotem2012-10-041-3/+35
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165267 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: locate user-defined text sections next to default text.Jim Grosbach2012-10-041-0/+21
| | | | | | | | | | | | Make sure functions located in user specified text sections (via the section attribute) are located together with the default text sections. Otherwise, for large object files, the relocations for call instructions are more likely to be out of range. This becomes even more likely in the presence of LTO. rdar://12402636 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165254 91177308-0d34-0410-b5e6-96231b3b80d8
* Update this a bit more to represent how the prologue should work:Eric Christopher2012-10-041-0/+35
| | | | | | | | | | a) frame setup instructions define the prologue b) we shouldn't change our location mid-stream Add a test to make sure that the stack adjustment stays within the prologue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165250 91177308-0d34-0410-b5e6-96231b3b80d8
* SimplifyCFG: Enhance the "remove CFG edge that leads to null pointer ↵Benjamin Kramer2012-10-041-0/+28
| | | | | | | | | | dereference" optimization to also handle instructions with multiple uses. We conservatively only check the first use to avoid walking long use chains. This catches the common case of having both a load and a store to a pointer supplied by a PHI node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165232 91177308-0d34-0410-b5e6-96231b3b80d8
* In my recent change to avoid use of underaligned memory I didn't notice thatDuncan Sands2012-10-041-2/+2
| | | | | | | | | cpyDest can be mutated in some cases, which would then cause a crash later if indeed the memory was underaligned. This brought down several buildbots, so I guess the underaligned case is much more common than I thought! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165228 91177308-0d34-0410-b5e6-96231b3b80d8
* The alignment of an sret parameter is known: it must be at least theDuncan Sands2012-10-041-0/+16
| | | | | | | alignment of the return type. Teach the optimizers this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165226 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR13969, a mini-phase-ordering issue with the new SROA pass.Chandler Carruth2012-10-041-0/+24
| | | | | | | | | | | | | | | | | | | | | Currently, we re-visit allocas when something changes about the way they might be *split* to allow better scalarization to take place. However, we weren't handling the case when the *promotion* is what would change the behavior of SROA. When an address derived from an alloca is stored into another alloca, we consider the first to have escaped. If the second is ever promoted to an SSA value, we will suddenly be able to run the SROA pass on the first alloca. This patch adds explicit support for this form if iteration. When we detect a store of a pointer derived from an alloca, we flag the underlying alloca for reprocessing after promotion. The logic works hard to only do this when there is definitely going to be promotion and it might remove impediments to the analysis of the alloca. Thanks to Nick for the great test case and Benjamin for some sanity check review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165223 91177308-0d34-0410-b5e6-96231b3b80d8
* The memcpy optimizer was happily doing call slot forwarding when the new memoryDuncan Sands2012-10-041-3/+21
| | | | | | | | | | | was less aligned than the old. In the testcase this results in an overaligned memset: the memset alignment was correct for the original memory but is too much for the new memory. Fix this by either increasing the alignment of the new memory or bailing out if that isn't possible. Should fix the gcc-4.7 self-host buildbot failure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165220 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the integer-promotion rewrite strategy to be endianness aware.Chandler Carruth2012-10-046-5/+113
| | | | | | | | | | | | | | | | | | | | | | | Sorry for this being broken so long. =/ As part of this, switch all of the existing tests to be Little Endian, which is the behavior I was asserting in them anyways! Add in a new big-endian test that checks the interesting behavior there. Another part of this is to tighten the rules abotu when we perform the full-integer promotion. This logic now rejects cases where there fully promoted integer is a non-multiple-of-8 bitwidth or cases where the loads or stores touch bits which are in the allocated space of the alloca but are not loaded or stored when accessing the integer. Sadly, these aren't really observable today as the rest of the pass will already ensure the invariants hold. However, the latter situation is likely to become a potential concern in the future. Thanks to Benjamin and Duncan for early review of this patch. I'm still looking into whether there are further endianness issues, please let me know if anyone sees BE failures persisting past this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165219 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement methods that enable expansion of load immediate Jack Carter2012-10-041-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | macro instruction (li) in the assembler. We have identified three possible expansions depending on the size of immediate operand: 1) for 0 ≤ j ≤ 65535. li d,j => ori d,$zero,j 2) for −32768 ≤ j < 0. li d,j => addiu d,$zero,j 3) for any other value of j that is representable as a 32-bit integer. li d,j => lui d,hi16(j) ori d,d,lo16(j) All of the above have been implemented in ths patch. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165199 91177308-0d34-0410-b5e6-96231b3b80d8
* This patch is a partial implementation of mips .set assembler directive. ↵Jack Carter2012-10-041-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Directive is defined as follows: .set option The patch implements following options at - lets the assembler use the $at register for macros, but generates warnings if the source program uses $at noat - let source programs use $at without issuingwarnings. noreorder - prevents the assembler from reordering machine language instructions. nomacro - causes the assembler to print a warning whenever an assembler operation generates more than one machine language instruction. macro - lets the assembler generate multiple machine instructions from a single assembler instruction reorder - lets the assembler reorder machine language instructions to improve performance The above variants are parsed and their boolean values set or unset. The code to actually use them will come later. Following options are not implemented yet: nomips16 nomicromips move nomove Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165194 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR13967.Jakub Staszak2012-10-031-0/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165187 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Add support in the X86AsmPrinter for printing memory referencesChad Rosier2012-10-031-0/+14
| | | | | | | | | | | | in the Intel syntax. The MC layer supports emitting in the Intel syntax, but this would require the inline assembly MachineInstr to be lowered to an MCInst before emission. This is potential future work, but for now emitting directly from the MachineInstr suffices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165173 91177308-0d34-0410-b5e6-96231b3b80d8
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