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* [XCore] Add LDAPB instructions.Richard Osborne2013-05-051-0/+6
| | | | | | | With the change the disassembler now supports the XCore ISA in its entirety. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181155 91177308-0d34-0410-b5e6-96231b3b80d8
* [XCore] Add BLRB instructions.Richard Osborne2013-05-051-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181152 91177308-0d34-0410-b5e6-96231b3b80d8
* For ARM backend, fixed "byval" attribute support.Stepan Dyatkovskiy2013-05-053-0/+166
| | | | | | | | | | | | | | | | | | | | | | | | | Now even the small structures could be passed within byval (small enough to be stored in GPRs). In regression tests next function prototypes are checked: PR15293: %artz = type { i32 } define void @foo(%artz* byval %s) define void @foo2(%artz* byval %s, i32 %p, %artz* byval %s2) foo: "s" stored in R0 foo2: "s" stored in R0, "s2" stored in R2. Next AAPCS rules are checked: 5.5 Parameters Passing, C.4 and C.5, "ParamSize" is parameter size in 32bit words: -- NSAA != 0, NCRN < R4 and NCRN+ParamSize > R4. Parameter should be sent to the stack; NCRN := R4. -- NSAA != 0, and NCRN < R4, NCRN+ParamSize < R4. Parameter stored in GPRs; NCRN += ParamSize. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181148 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a recently redundant transform from X86ISelLowering.David Majnemer2013-05-051-4/+1
| | | | | | | | | | | | | X86ISelLowering has support to treat: (icmp ne (and (xor %flags, -1), (shl 1, flag)), 0) as if it were actually: (icmp eq (and %flags, (shl 1, flag)), 0) However, r179386 has code at the InstCombine level to handle this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181145 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorize: Add support for floating point min/max reductionsArnold Schwaighofer2013-05-051-0/+480
| | | | | | | | | | Add support for min/max reductions when "no-nans-float-math" is enabled. This allows us to assume we have ordered floating point math and treat ordered and unordered predicates equally. radar://13723044 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181144 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorize: We don't need an identity element for min/max reductionsArnold Schwaighofer2013-05-051-1/+4
| | | | | | | | | | We can just use the initial element that feeds the reduction. max(max(x, y), z) == max(max(x,y), max(x,z)) radar://13723044 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181141 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: enable MCJIT and tests now that everything passes.Tim Northover2013-05-041-3/+4
| | | | | | | This removes dire warnings about AArch64 being unsupported and enables the tests when appropriate on this platform. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181135 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: support literal pool access in large memory model.Tim Northover2013-05-041-0/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181120 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: support large code model for jump-tablesTim Northover2013-05-041-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181119 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: implement support for blockaddress in large code modelTim Northover2013-05-041-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181118 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: implement large code model access to global variables.Tim Northover2013-05-042-0/+80
| | | | | | | | | | | | | | The MOVZ/MOVK instruction sequence may not be the most efficient (a literal-pool load could be better) but adding that would require reinstating the ConstantIslands pass. For now the sequence is correct, and that's enough. Beware, as of commit GNU ld does not appear to support the relocations needed for this. Its primary purpose (for now) will be to support JITed code, since in that case there is no guarantee of where your code will end up in memory relative to external symbols it references. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181117 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow host triple to be correctly overridden in CMake buildsTim Northover2013-05-042-2/+2
| | | | | | | | | | | The intended semantics mirror autoconf, where the user is able to specify a host triple, but if it's left to the build system then "config.guess" is invoked for the default. This also renames the LLVM_HOSTTRIPLE define to LLVM_HOST_TRIPLE to fit in with the style of the surrounding defines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181112 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r181009.Amara Emerson2013-05-032-0/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181079 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some uneeded pseudos in the presence of the naked function attribute.Reed Kotler2013-05-031-0/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181072 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete test instead.Amara Emerson2013-05-031-47/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181066 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily disable failing test.Amara Emerson2013-05-031-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181062 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Parse platform-specifc variant kinds in AsmParserUlrich Weigand2013-05-031-0/+95
| | | | | | | | | | | This patch adds support for PowerPC platform-specific variant kinds in MCSymbolRefExpr::getVariantKindForName, and also adds a test case to verify they are translated to the appropriate fixup type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181053 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Add some Book II instructions to AsmParserUlrich Weigand2013-05-031-0/+58
| | | | | | | | | | | | | | | This patch adds a couple of Book II instructions (isync, icbi) to the PowerPC assembler parser. These are needed when bootstrapping clang with the integrated assembler forced on, because they are used in inline asm statements in the code base. The test case adds the full list of Book II storage control instructions, including associated extended mnemonics. Again, those that are not yet supported as marked as FIXME. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181052 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Support extended mnemonics in AsmParserUlrich Weigand2013-05-031-0/+331
| | | | | | | | | | | | | | This patch adds infrastructure to support extended mnemonics in the PowerPC assembler parser. It adds support specifically for those extended mnemonics that LLVM will itself generate. The test case lists *all* extended mnemonics according to the PowerPC ISA v2.06 Book I, but marks those not yet supported as FIXME. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181051 91177308-0d34-0410-b5e6-96231b3b80d8
* [PowerPC] Add assembler parserUlrich Weigand2013-05-035-0/+1294
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds assembler parser support to the PowerPC back end. The parser will run for any powerpc-*-* and powerpc64-*-* triples, but was tested only on 64-bit Linux. The supported syntax is intended to be compatible with the GNU assembler. The parser does not yet support all PowerPC instructions, but it does support anything that is generated by LLVM itself. There is no support for testing restricted instruction sets yet, i.e. the parser will always accept any instructions it knows, no matter what feature flags are given. Instruction operands will be checked for validity and errors generated. (Error handling in general could still be improved.) The patch adds a number of test cases to verify instruction and operand encodings. The tests currently cover all instructions from the following PowerPC ISA v2.06 Book I facilities: Branch, Fixed-point, Floating-Point, and Vector. Note that a number of these instructions are not yet supported by the back end; they are marked with FIXME. A number of follow-on check-ins will add extra features. When they are all included, LLVM passes all tests (including bootstrap) when using clang -cc1as as the system assembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181050 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Split the DSP control register and define one register for each field ofAkira Hatanaka2013-05-031-8/+3
| | | | | | | | | | | | | its fields. This removes false dependencies between DSP instructions which access different fields of the the control register. Implicit register operands are added to instructions RDDSP and WRDSP after instruction selection, depending on the value of the mask operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181041 91177308-0d34-0410-b5e6-96231b3b80d8
* LoopVectorizer: Add support for if-conversion of PHINodes with 3+ incoming ↵Nadav Rotem2013-05-031-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | values. By supporting the vectorization of PHINodes with more than two incoming values we can increase the complexity of nested if statements. We can now vectorize this loop: int foo(int *A, int *B, int n) { for (int i=0; i < n; i++) { int x = 9; if (A[i] > B[i]) { if (A[i] > 19) { x = 3; } else if (B[i] < 4 ) { x = 4; } else { x = 5; } } A[i] = x; } } git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181037 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Expand vector or, shl, srl, and xor nodesTom Stellard2013-05-034-0/+52
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181035 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add pattern for SHA-256 Ma functionTom Stellard2013-05-031-0/+18
| | | | | | This can be optimized using the BFI_INT instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181033 91177308-0d34-0410-b5e6-96231b3b80d8
* RegionInfo: Do not crash if unreachable block is foundTobias Grosser2013-05-031-0/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181025 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for reading ARM ELF build attributes.Amara Emerson2013-05-033-0/+46
| | | | | | | | | | | | Build attribute sections can now be read if they exist via ELFObjectFile, and the llvm-readobj tool has been extended with an option to dump this information if requested. Regression tests are also included which exercise these features. Also update the docs with a fixed ARM ABI link and a new link to the Addenda which provides the build attributes specification. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181009 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Handle reading, writing or copying of ccond field of DSP controlAkira Hatanaka2013-05-021-0/+20
| | | | | | | | | | | | | register. - Define pseudo instructions which store or load ccond field of the DSP control register. - Emit the pseudos in MipsSEInstrInfo::storeRegToStack and loadRegFromStack. - Expand the pseudos before callee-scan save. - Emit instructions RDDSP or WRDSP to copy between ccond field and GPRs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180969 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Signed literals are 64bits wideVincent Lejeune2013-05-021-0/+165
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180960 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: If previous bundle is dot4, PV valid chan is always XVincent Lejeune2013-05-021-0/+244
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180959 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add a test to check that use_kill is emittedVincent Lejeune2013-05-021-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180958 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Prettier asmPrint of AluVincent Lejeune2013-05-0234-101/+127
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180956 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon - Add peephole optimizations for zero extends.Pranav Bhandarkar2013-05-022-6/+24
| | | | | | | | | | | | | | * lib/Target/Hexagon/HexagonInstrInfo.td: Add patterns to combine a sequence of a pair of i32->i64 extensions followed by a "bitwise or" into COMBINE_rr. * lib/Target/Hexagon/HexagonPeephole.cpp: Copy propagate Rx in the instruction Rp = COMBINE_Ir_V4(0, Rx) to the uses of Rp:subreg_loreg. * test/CodeGen/Hexagon/union-1.ll: New test. * test/CodeGen/Hexagon/combine_ir.ll: Fix test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180946 91177308-0d34-0410-b5e6-96231b3b80d8
* TBAA: remove !tbaa from testing cases if not used.Manman Ren2013-05-029-182/+138
| | | | | | | | This will make it easier to turn on struct-path aware TBAA since the metadata format will change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180935 91177308-0d34-0410-b5e6-96231b3b80d8
* Rewrite X86 codegen regression test with FileCheckMichael Liao2013-05-021-4/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180910 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a test for the foldSelectICmpAndOr fix committed in r180779.David Majnemer2013-05-021-0/+13
| | | | | | | | This tests a case where C1 and C2 were the same but X and Y were different widths. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180907 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid generating tempfile(s) never usedMichael Liao2013-05-011-2/+2
| | | | | | | | As DejaGNU is deprecated, it seems pipe-jam issue doesn't exist any more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180892 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r180737. The companion patch was reverted, and this is not relevant ↵Bill Wendling2013-05-011-89/+0
| | | | | | right now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180889 91177308-0d34-0410-b5e6-96231b3b80d8
* SROA: Generate selects instead of shuffles when blending values because this ↵Nadav Rotem2013-05-011-14/+14
| | | | | | | | | | is the cannonical form. Shuffles are more difficult to lower and we usually don't touch them, while we do optimize selects more often. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180875 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize away nop CONCAT_VECTOR nodes.Nadav Rotem2013-05-011-0/+13
| | | | | | | | | | | Optimize CONCAT_VECTOR nodes that merge EXTRACT_SUBVECTOR values that extract from the same vector. rdar://13402653 PR15866 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180871 91177308-0d34-0410-b5e6-96231b3b80d8
* Put VMOVPQIto64rr in the VRPDI class.Rafael Espindola2013-05-011-0/+10
| | | | | | Patch by Joshua Magee. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180842 91177308-0d34-0410-b5e6-96231b3b80d8
* Forget remove the tempfile argumentMichael Liao2013-05-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180838 91177308-0d34-0410-b5e6-96231b3b80d8
* More rewrites of x86 codegen regression tests with FileCheckMichael Liao2013-05-0119-28/+78
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180837 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "InstCombine: Fold more shuffles of shuffles."Jim Grosbach2013-05-012-10/+11
| | | | | | | | | This reverts commit r180802 There's ongoing discussion about whether this is the right place to make this transformation. Reverting for now while we figure it out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180834 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix handling of instructions which copy to/from accumulator registers.Akira Hatanaka2013-04-301-0/+21
| | | | | | | | | | | Expand copy instructions between two accumulator registers before callee-saved scan is done. Handle copies between integer GPR and hi/lo registers in MipsSEInstrInfo::copyPhysReg. Delete pseudo-copy instructions that are not needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180827 91177308-0d34-0410-b5e6-96231b3b80d8
* Only pass 'returned' to target-specific lowering code when the value of ↵Stephen Lin2013-04-302-64/+178
| | | | | | entire register is guaranteed to be preserved. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180825 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Instruction selection patterns for DSP-ASE vector select and compareAkira Hatanaka2013-04-301-0/+641
| | | | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180820 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily revert "Change the informal convention of DBG_VALUE so that we ↵Adrian Prantl2013-04-306-119/+9
| | | | | | | | | | can express a" because it breaks some buildbots. This reverts commit 180816. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180819 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the informal convention of DBG_VALUE so that we can express aAdrian Prantl2013-04-306-9/+119
| | | | | | | | | | | | register-indirect address with an offset of 0. It used to be that a DBG_VALUE is a register-indirect value if the offset (operand 1) is nonzero. The new convention is that a DBG_VALUE is register-indirect if the first operand is a register and the second operand is an immediate. For plain registers use the combination reg, reg. rdar://problem/13658587 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180816 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Test for r179873.Akira Hatanaka2013-04-301-0/+64
| | | | | | | | Patch by Zoran Jovanovic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180804 91177308-0d34-0410-b5e6-96231b3b80d8
* InstCombine: Fold more shuffles of shuffles.Jim Grosbach2013-04-302-11/+10
| | | | | | | | | | | Always fold a shuffle-of-shuffle into a single shuffle when there's only one input vector in the first place. Continue to be more conservative when there's multiple inputs. rdar://13402653 PR15866 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180802 91177308-0d34-0410-b5e6-96231b3b80d8
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