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* Cleanup the stackmap operand folding code and fix a corner case.Andrew Trick2013-11-121-1/+21
| | | | | | | I still don't know how to refer to the fixed operands symbolically. I plan to look into it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194529 91177308-0d34-0410-b5e6-96231b3b80d8
* improve dependence analysis testcasesSebastian Pop2013-11-123-1/+30
| | | | | | | print the name of the function on which the dependence analysis is performed such that changes to the testcase are easier to review. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194528 91177308-0d34-0410-b5e6-96231b3b80d8
* delinearization of arraysSebastian Pop2013-11-1211-0/+751
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194527 91177308-0d34-0410-b5e6-96231b3b80d8
* Fold (iszero(A&K1) | iszero(A&K2)) -> (A&(K1|K2)) != (K1|K2) if we know ↵Nadav Rotem2013-11-121-0/+35
| | | | | | that K1 and K2 are 'one-hot' (only one bit is on). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194525 91177308-0d34-0410-b5e6-96231b3b80d8
* FoldBranchToCommonDest merges branches into a single branch with or/and of ↵Nadav Rotem2013-11-121-0/+29
| | | | | | the condition. It has a heuristics for estimating when some of the dependencies are processed by out-of-order processors. This patch adds another rule to the heuristics that says that if the "BonusInstruction" that we speculatively execute is used by the condition of the second branch then it is okay to hoist it. This change exposes more opportunities for other passes to transform the code. It does not matter that much that we if-convert the code because the selectiondag builder splits or/and branches into multiple branches when profitable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194524 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix a bug in function CC_MipsO32_FP64. The second double precisionAkira Hatanaka2013-11-121-6/+6
| | | | | | | | argument was not being passed in $f14. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194522 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Run test case with command line option -mattr=+fp64.Akira Hatanaka2013-11-121-16/+39
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194519 91177308-0d34-0410-b5e6-96231b3b80d8
* Protect user-supplied runtime library functions in LTOJustin Bogner2013-11-121-0/+27
| | | | | | | | | | | | | | Add user-supplied C runtime and compiler-rt library functions to llvm.compiler.used to protect them from premature optimization by passes like -globalopt and -ipsccp. Calls to (seemingly unused) runtime library functions can be added by -instcombine and instruction lowering. Patch by Duncan Exon Smith, thanks! Fixes <rdar://problem/14740087> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194514 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: diagnose invalid system LDM/STMTim Northover2013-11-121-0/+5
| | | | | | | | | | | | | The system LDM and STM instructions can't usually writeback to the base register. The one exception is when an LDM is actually an exception-return (i.e. contains PC in the register list). (There's already a test that "ldm sp!, {r0-r3, pc}^" works, which is why there is no positive test). rdar://problem/15223374 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194512 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix and re-enable a test case that has been disabled for a long time.Akira Hatanaka2013-11-121-99/+120
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194510 91177308-0d34-0410-b5e6-96231b3b80d8
* [OCaml] Dynamically link LLVM on --enable-shared buildsPeter Zotov2013-11-121-1/+1
| | | | | | | | | | This commit significantly speeds up both bytecode and native builds of LLVM clients (from ~20 second to sub-second link time), and allows to invoke LLVM functions from OCaml toplevel. The behavior for --disable-shared builds is unchanged. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194509 91177308-0d34-0410-b5e6-96231b3b80d8
* Corruptly merge constants with explicit and implicit alignments.Rafael Espindola2013-11-121-0/+28
| | | | | | | | | | | | | Constant merge can merge a constant with implicit alignment with one that has explicit alignment. Before this change it was assuming that the explicit alignment was higher than the implicit one, causing the result to be under aligned in some cases. Fixes pr17815. Patch by Chris Smowton! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194506 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Implemented AdvSIMD scalar x indexed element format and AdvSIMD scalarChad Rosier2013-11-1210-6/+674
| | | | | | | | copy in MC layer. Added the MC layer tests. Fixed triple setting in test cases. Patch by Ana Pazos <apazos@codeaurora.org>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194501 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify operand folding when rematerializing a load.Andrew Trick2013-11-121-11/+6
| | | | | | | | | | | | We already know how to fold a reload from a frameindex without analyzing the load instruction. Generalize this to handle any frameindex load. This streamlines the logic for rematerializing loads from stack arguments. As a side effect, it allows stackmaps to record a stack argument location without spilling it. Verified no effect on codegen for llvm test-suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194497 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Enable inlinse assembly for MSA.Daniel Sanders2013-11-121-0/+34
| | | | | | | | | | | | | | | | Like GCC, this re-uses the 'f' constraint and a new 'w' print-modifier: asm ("ldi.w %w0, 1", "=f"(result)); Unlike GCC, the 'w' print-modifer is not _required_ to produce the intended output. This is a consequence of differences in the internal handling of the registers in each compiler. To be source-compatible between the compilers, users must use the 'w' print-modifier. MSA registers (including control registers) are supported in clobber lists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194476 91177308-0d34-0410-b5e6-96231b3b80d8
* SimplifyCFG: Use existing constant folding logic when forming switch tables.Benjamin Kramer2013-11-121-3/+6
| | | | | | Both simpler and more powerful than the hand-rolled folding logic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194475 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. ↵Daniel Sanders2013-11-122-1/+139
| | | | | | not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194471 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Add support for FP_HP_extension build attributeBradley Smith2013-11-122-6/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194470 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Added support for matching bset, bseti, bneg, and bnegi from ↵Daniel Sanders2013-11-121-0/+248
| | | | | | normal IR (i.e. not intrinsics) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194469 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] Change constant used in ori tests to avoid conflict with bseti ↵Daniel Sanders2013-11-121-16/+16
| | | | | | | | | | | | | | (also xori to avoid bnegi) Upcoming commit(s) are going to add support for bseti and bnegi. This would cause some existing tests to (correctly) change behaviour and emit a different instruction. This patch prevents this by changing the constant used in ori and xori tests so that they will not be matchable by the bseti and bnegi patterns when these instructions are matchable from normal IR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194467 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: fix bug in aligning 'byval i8*' on the stackRobert Lytton2013-11-121-0/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194466 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target test for hidden declarationRobert Lytton2013-11-121-1/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194465 91177308-0d34-0410-b5e6-96231b3b80d8
* Add XCore support for ATOMIC_FENCE.Robert Lytton2013-11-121-0/+16
| | | | | | | | | | ATOMIC_FENCE is lowered to a compiler barrier which is codegen only. There is no need to emit an instructions since the XCore provides sequential consistency. Original patch by Richard Osborne git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194464 91177308-0d34-0410-b5e6-96231b3b80d8
* XCore target: return error for unsupported alignmentRobert Lytton2013-11-121-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194463 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Added basic unit test for llvm-cov."Yuchen Wu2013-11-127-169/+0
| | | | | | | | | | | This reverts commit r194451. Not sure why the tests are failing on the buildbot. They run fine on my local machine. Could it possibly be because of the endianness of the architectures? The GCNO and GCDA files are little-endian encoded, and llvm-cov expects it to remain that way. Is this a safe assumption? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194454 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-cov: Added call to update run/program counts.Yuchen Wu2013-11-122-0/+0
| | | | | | Also updated test files that were generated from this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194453 91177308-0d34-0410-b5e6-96231b3b80d8
* Added basic unit test for llvm-cov.Yuchen Wu2013-11-127-0/+169
| | | | | | | | | This test compares the output of llvm-cov against a coverage file generated by gcov. Since the source file must be in the current directory when reading GCNO files, the test will first cd into the Inputs directory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194451 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Change formatting of printed registers.Matt Arsenault2013-11-1253-280/+279
| | | | | | | | | | | | | | | | | | | | | | | Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194443 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the default branch instruction to be the 16 bit variety for mips16.Reed Kotler2013-11-121-0/+37
| | | | | | | | | | | | | This has no material effect at this time since we don't have a direct object emitter for mips16 and the assembler can't tell them apart. I place a comment "16 bit inst" for those so that I can tell them apart in the output. The constant island pass has only been minimally changed to allow this. More complete branch work is forthcoming but this is the first step. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194442 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add test that fails due to requiring i64 mul for pointersMatt Arsenault2013-11-111-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194433 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the recently added anyregcc convention to handle spilled operands.Andrew Trick2013-11-111-8/+37
| | | | | | | | | | | | Fixes <rdar://15432754> [JS] Assertion: "Folded a def to a non-store!" The primary purpose of anyregcc is to prevent a patchpoint's call arguments and return value from being spilled. They must be available in a register, although the calling convention does not pin the register. It's up to the front end to avoid using this convention for calls with more arguments than allocatable registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194428 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use function inputs to represent data stored in gprVincent Lejeune2013-11-1125-280/+246
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194425 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR17952.Shuxin Yang2013-11-118-22/+221
| | | | | | | | | | | | | | | | | | | | | | | | The symptom is that an assertion is triggered. The assertion was added by me to detect the situation when value is propagated from dead blocks. (We can certainly get rid of assertion; it is safe to do so, because propagating value from dead block to alive join node is certainly ok.) The root cause of this bug is : edge-splitting is conducted on the fly, the edge being split could be a dead edge, therefore the block that split the critial edge needs to be flagged "dead" as well. There are 3 ways to fix this bug: 1) Get rid of the assertion as I mentioned eariler 2) When an dead edge is split, flag the inserted block "dead". 3) proactively split the critical edges connecting dead and live blocks when new dead blocks are revealed. This fix go for 3) with additional 2 LOC. Testing case was added by Rafael the other day. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194424 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Partially revert r193641. Stack alignment should not be determined byAkira Hatanaka2013-11-111-2/+1
| | | | | | | | the floating point register mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194423 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for DT_VERxxx and DT_MIPS_xxx .dynamic section entries to theSimon Atanasyan2013-11-113-0/+40
| | | | | | | | | llvm-readobj. The patch reviewed by Michael Spencer. http://llvm-reviews.chandlerc.com/D2113 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194421 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Add support for MVFR2 which is new in ARMv8Artyom Skrobov2013-11-113-0/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194416 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Properly handle bitcast ConstantExpr when checking for the alignment ↵Justin Holewinski2013-11-111-0/+26
| | | | | | of function parameters git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194410 91177308-0d34-0410-b5e6-96231b3b80d8
* [NVPTX] Fix logic error in loading vector parameters of more than 4 componentsJustin Holewinski2013-11-111-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194409 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] The shift right/left and insert immediate builtins expect 3Chad Rosier2013-11-111-14/+18
| | | | | | source operands, a vector, an element to insert, and a shift amount. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194406 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar floating-point convert to fixed-point ↵Chad Rosier2013-11-114-8/+128
| | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194394 91177308-0d34-0410-b5e6-96231b3b80d8
* Vector forms of SHL, SRA, and SRL can be constant folded using ↵Daniel Sanders2013-11-111-0/+70
| | | | | | | | | | | | | | SimplifyVBinOp too Reviewers: dsanders Reviewed By: dsanders CC: llvm-commits, nadav Differential Revision: http://llvm-reviews.chandlerc.com/D1958 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194393 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] CHECK-DAG-ize MSA 3r-a.ll test.Matheus Almeida2013-11-111-192/+336
| | | | | | | | No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194391 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] CHECK-DAG-ize MSA 2rf_int_float.ll test.Matheus Almeida2013-11-111-30/+50
| | | | | | | | No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194390 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] CHECK-DAG-ize MSA 2rf_float_int.ll test.Matheus Almeida2013-11-111-12/+20
| | | | | | | | No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194389 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] CHECK-DAG-ize MSA 2rf.ll test.Matheus Almeida2013-11-111-48/+80
| | | | | | | | No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194387 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips][msa] CHECK-DAG-ize MSA 2r.ll test.Matheus Almeida2013-11-111-36/+60
| | | | | | | | No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194386 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a testcase for pr17852.Rafael Espindola2013-11-111-0/+66
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194385 91177308-0d34-0410-b5e6-96231b3b80d8
* Add PPC option for full register names in asmHal Finkel2013-11-111-0/+17
| | | | | | | | | | | | | | | | | | | | | On non-Darwin PPC systems, we currently strip off the register name prefix prior to instruction printing. So instead of something like this: mr r3, r4 we print this: mr 3, 4 The first form is the default on Darwin, and is understood by binutils, but not yet understood by our integrated assembler. Once our integrated-as understands full register names as well, this temporary option will be replaced by tying this functionality to the verbose-asm option. The numeric-only form is compatible with legacy assemblers and tools, and is also gcc's default on most PPC systems. On the other hand, it is harder to read, and there are some analysis tools that expect full register names. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194384 91177308-0d34-0410-b5e6-96231b3b80d8
* [OCaml] Add missing Llvm_target functionsPeter Zotov2013-11-111-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194382 91177308-0d34-0410-b5e6-96231b3b80d8
* [OCaml] Accept context explicitly in Llvm_target functionsPeter Zotov2013-11-112-2/+2
| | | | | | | | Llvm_target.intptr_type used to implicitly use global context. As none of other functions in OCaml bindings do, it is changed to accept context explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194381 91177308-0d34-0410-b5e6-96231b3b80d8
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