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path: root/utils/TableGen/CodeEmitterGen.cpp
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* Tidy up a bit.Jim Grosbach2011-02-031-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124832 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a comment typo.Bob Wilson2011-01-271-1/+1
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* Change all self assignments X=X to (void)X, so that we can turn on aJeffrey Yasskin2010-12-231-1/+1
| | | | | | | | | new gcc warning that complains on self-assignments and self-initializations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122458 91177308-0d34-0410-b5e6-96231b3b80d8
* Move <map> include out of .h and into .cpp.Bill Wendling2010-12-131-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121661 91177308-0d34-0410-b5e6-96231b3b80d8
* eliminate the Records global variable, patch by Garrison Venn!Chris Lattner2010-12-131-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121659 91177308-0d34-0410-b5e6-96231b3b80d8
* pull the code to get the operand value out of the loop.Chris Lattner2010-11-151-48/+58
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119130 91177308-0d34-0410-b5e6-96231b3b80d8
* split the giant encoder loop into two new helper functions.Chris Lattner2010-11-151-112/+122
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119129 91177308-0d34-0410-b5e6-96231b3b80d8
* reduce nesting and minor cleanups, no functionality change.Chris Lattner2010-11-151-87/+88
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119128 91177308-0d34-0410-b5e6-96231b3b80d8
* add fields to the .td files unconditionally, simplifying tblgen a bit.Chris Lattner2010-11-151-3/+3
| | | | | | | | Switch the ARM backend to use 'let' instead of 'set' with this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119120 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for specifying a PostEncoderMethod, which can perform ↵Owen Anderson2010-11-111-0/+4
| | | | | | | | | post-processing after the automated encoding of an instruction. Not yet used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118759 91177308-0d34-0410-b5e6-96231b3b80d8
* Support generating an MC'ized CodeEmitter directly. Maintain a reference to theJim Grosbach2010-11-031-5/+18
| | | | | | | Fixups list for the instruction so the operand encoders can add to it as needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118206 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r114340 (improvements in Darwin function prologue/epilogue), as it brokeJim Grosbach2010-11-021-0/+6
| | | | | | assumptions about stack layout. Specifically, LR must be saved next to FP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118026 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up.Jim Grosbach2010-11-021-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117987 91177308-0d34-0410-b5e6-96231b3b80d8
* factor the operand list (and related fields/operations) out of Chris Lattner2010-11-011-6/+7
| | | | | | | CodeGenInstruction into its own helper class. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117893 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow targets to optionally specify custom binary encoder functions forJim Grosbach2010-10-121-5/+20
| | | | | | | | | | operand values. This is useful for operands which require additional trickery to encode into the instruction. For example, the ARM shifted immediate and shifted register operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116353 91177308-0d34-0410-b5e6-96231b3b80d8
* The assert() should reference to machine instr operand number, too.Jim Grosbach2010-10-111-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116243 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure to use the machine instruction operand number. It doesn't alwaysJim Grosbach2010-10-111-0/+2
| | | | | | map one-to-one with the CodeGenInstruction operand number. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116238 91177308-0d34-0410-b5e6-96231b3b80d8
* When figuring out which operands match which encoding fields in an instruction,Jim Grosbach2010-10-111-6/+17
| | | | | | | | | try to match them by name first. If there is no by-name match, fall back to assuming they are in order (this was the previous behavior). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116211 91177308-0d34-0410-b5e6-96231b3b80d8
* Make <target>CodeEmitter::getBinaryCodeForInstr() a const method.Jim Grosbach2010-10-081-1/+1
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* trailing whitespaceJim Grosbach2010-10-071-17/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115923 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up TargetOpcodes.h a bit, and limit the number of places where the fullJakob Stoklund Olesen2010-07-021-40/+5
| | | | | | | | | list of predefined instructions appear. Add some consistency checks. Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it is hardly worth the effort. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107520 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a pseudo instruction REG_SEQUENCE that takes a list of registers andEvan Cheng2010-05-011-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sub-register indices and outputs a single super register which is formed from a consecutive sequence of registers. This is used as register allocation / coalescing aid and it is useful to represent instructions that output register pairs / quads. For example, v1024, v1025 = vload <address> where v1024 and v1025 forms a register pair. This really should be modelled as v1024<3>, v1025<4> = vload <address> but it would violate SSA property before register allocation is done. Currently we use insert_subreg to form the super register: v1026 = implicit_def v1027 - insert_subreg v1026, v1024, 3 v1028 = insert_subreg v1027, v1025, 4 ... = use v1024 = use v1028 But this adds pseudo live interval overlap between v1024 and v1025. We can now modeled it as v1024, v1025 = vload <address> v1026 = REG_SEQUENCE v1024, 3, v1025, 4 ... = use v1024 = use v1026 After coalescing, it will be v1026<3>, v1025<4> = vload <address> ... = use v1026<3> = use v1026 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102815 91177308-0d34-0410-b5e6-96231b3b80d8
* rename llvm::llvm_report_error -> llvm::report_fatal_errorChris Lattner2010-04-071-1/+1
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* change Target.getInstructionsByEnumValue to return a referenceChris Lattner2010-03-191-3/+3
| | | | | | | | to a vector that CGT stores instead of synthesizing it on every call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98910 91177308-0d34-0410-b5e6-96231b3b80d8
* look up instructions by record, not by name.Chris Lattner2010-03-191-1/+1
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* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-091-3/+3
| | | | | | | | | | into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove DEBUG_DECLARE, looks like we don't need it.Dale Johannesen2010-01-151-6/+3
| | | | | | | | Also, DEBUG_VALUE has side effects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93498 91177308-0d34-0410-b5e6-96231b3b80d8
* Add DEBUG_DECLARE. Not used yet.Dale Johannesen2010-01-091-3/+6
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* Add DEBUG_VALUE. Not used yet.Dale Johannesen2010-01-081-3/+6
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* Revert 90628, which was incorrect.Dan Gohman2009-12-151-6/+9
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* Minor code simplification.Dan Gohman2009-12-051-9/+6
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* Introduce the TargetInstrInfo::KILL machine instruction and get rid of theJakob Stoklund Olesen2009-09-281-3/+3
| | | | | | | | | | unused DECLARE instruction. KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF in the places where IMPLICIT_DEF is just used to alter liveness of physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83006 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert more abort() calls to llvm_report_error().Torok Edwin2009-07-081-2/+4
| | | | | | | Also remove trailing semicolon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75027 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace std::iostreams with raw_ostream in TableGen.Daniel Dunbar2009-07-031-1/+1
| | | | | | | | | - Sorry, I can't help myself. - No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74742 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename COPY_TO_SUBCLASS to COPY_TO_REGCLASS, and generalizeDan Gohman2009-04-131-3/+3
| | | | | | | | it accordingly. Thanks to Jakob Stoklund Olesen for pointing out how this might be useful. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68986 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new TargetInstrInfo MachineInstr opcode, COPY_TO_SUBCLASS.Dan Gohman2009-04-131-5/+8
| | | | | | | | | | | | | | | | | This will be used to replace things like X86's MOV32to32_. Enhance ScheduleDAGSDNodesEmit to be more flexible and robust in the presense of subregister superclasses and subclasses. It can now cope with the definition of a virtual register being in a subclass of a use. Re-introduce the code for recording register superreg classes and subreg classes. This is needed because when subreg extracts and inserts get coalesced away, the virtual registers are left in the correct subclass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68961 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix shift overflow bug that would occur when a field was a full 32-bits Chris Lattner2008-10-051-1/+1
| | | | | | | | in tblgen. This is PR2827, thanks to Waldemar Knorr for tracking this down. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57124 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction names as comments to InstBits entries.Evan Cheng2008-09-171-5/+3
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* Eliminate a compile time warning.Evan Cheng2008-09-071-1/+1
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* Change getBinaryCodeForInstr prototype. First operand MachineInstr& should ↵Evan Cheng2008-09-021-1/+2
| | | | | | be const. Make corresponding changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55623 91177308-0d34-0410-b5e6-96231b3b80d8
* Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminatingDan Gohman2008-07-011-3/+9
| | | | | | | | | | | | | | | | | the need for a flavor operand, and add a new SDNode subclass, LabelSDNode, for use with them to eliminate the need for a label id operand. Change instruction selection to let these label nodes through unmodified instead of creating copies of them. Teach the MachineInstr emitter how to emit a MachineInstr directly from an ISD label node. This avoids the need for allocating SDNodes for the label id and flavor value, as well as SDNodes for each of the post-isel label, label id, and label flavor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52943 91177308-0d34-0410-b5e6-96231b3b80d8
* Make insert_subreg a two-address instruction, vastly simplifying ↵Christopher Lamb2008-03-161-3/+6
| | | | | | LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48412 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace all target specific implicit def instructions with a target ↵Evan Cheng2008-03-151-3/+6
| | | | | | independent one: TargetInstrInfo::IMPLICIT_DEF. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
* SDIsel processes llvm.dbg.declare by recording the variable debug ↵Evan Cheng2008-02-021-0/+3
| | | | | | | | | | information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes. For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
* remove attributions from utils.Chris Lattner2007-12-291-2/+2
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* Add target independent MachineInstr's to represent subreg insert/extract in ↵Christopher Lamb2007-07-261-3/+9
| | | | | | MBB's. PR1350 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40518 91177308-0d34-0410-b5e6-96231b3b80d8
* Files missing from LABEL check in.Jim Laskey2007-01-261-3/+9
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* What should be the last unnecessary <iostream>s in the library.Bill Wendling2006-12-071-1/+1
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* Remove the isTwoAddress property from the CodeGenInstruction class. It shouldChris Lattner2006-11-151-9/+9
| | | | | | | | | | | not be used for anything other than backwards compat constraint handling. Add support for a new DisableEncoding property which contains a list of registers that should not be encoded by the generated code emitter. Convert the codeemitter generator to use this, fixing some PPC JIT regressions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31769 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove an unused variable.Reid Spencer2006-11-031-3/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31403 91177308-0d34-0410-b5e6-96231b3b80d8
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