aboutsummaryrefslogtreecommitdiffstats
path: root/utils/TableGen/CodeGenTarget.cpp
Commit message (Collapse)AuthorAgeFilesLines
...
* Added support for vector widening.Mon P Wang2008-12-181-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61209 91177308-0d34-0410-b5e6-96231b3b80d8
* Modify the intrinsics pattern to separate out the "return" types from theBill Wendling2008-11-131-16/+29
| | | | | | | | | | | | "parameter" types. An intrinsic can now return a multiple return values like this: def add_with_overflow : Intrinsic<[llvm_i32_ty, llvm_i1_ty], [LLVMMatchType<0>, LLVMMatchType<0>]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59237 91177308-0d34-0410-b5e6-96231b3b80d8
* Factor the code for determining the target-specific instructionDan Gohman2008-08-201-0/+15
| | | | | | | namespace out of the isel emitters and into common code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55079 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the string for MVT::isVoid.Dan Gohman2008-08-201-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55034 91177308-0d34-0410-b5e6-96231b3b80d8
* Added support for overloading intrinsics (atomics) based on pointersMon P Wang2008-07-301-1/+3
| | | | | | | | to different address spaces. This alters the naming scheme for those intrinsics, e.g., atomic.load.add.i32 => atomic.load.add.i32.p0i32 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54195 91177308-0d34-0410-b5e6-96231b3b80d8
* Split ISD::LABEL into ISD::DBG_LABEL and ISD::EH_LABEL, eliminatingDan Gohman2008-07-011-5/+17
| | | | | | | | | | | | | | | | | the need for a flavor operand, and add a new SDNode subclass, LabelSDNode, for use with them to eliminate the need for a label id operand. Change instruction selection to let these label nodes through unmodified instead of creating copies of them. Teach the MachineInstr emitter how to emit a MachineInstr directly from an ISD label node. This avoids the need for allocating SDNodes for the label id and flavor value, as well as SDNodes for each of the post-isel label, label id, and label flavor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52943 91177308-0d34-0410-b5e6-96231b3b80d8
* Added MemOperands to Atomic operations since Atomics touches memory.Mon P Wang2008-06-251-0/+2
| | | | | | | | | Added abstract class MemSDNode for any Node that have an associated MemOperand Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and atomic.lss => atomic.load.sub git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52706 91177308-0d34-0410-b5e6-96231b3b80d8
* - Add "Commutative" property to intrinsics. This allows tblgen to generate ↵Evan Cheng2008-06-161-0/+3
| | | | | | | | | the commuted variants for dagisel matching code. - Mark lots of X86 intrinsics as "Commutative" to allow load folding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52353 91177308-0d34-0410-b5e6-96231b3b80d8
* Wrap MVT::ValueType in a struct to get type safetyDuncan Sands2008-06-061-9/+9
| | | | | | | | | | | | | | | | | and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
* Move instruction flag inference out of InstrInfoEmitter and intoDan Gohman2008-04-031-10/+2
| | | | | | | | | | | | | CodeGenDAGPatterns, where it can be used in other tablegen backends. This allows the inference to be done for DAGISelEmitter so that it gets accurate mayLoad/mayStore/isSimpleLoad flags. This brings MemOperand functionality back to where it was before 48329. However, it doesn't solve the problem of anonymous patterns which expand to code that does loads or stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49123 91177308-0d34-0410-b5e6-96231b3b80d8
* Make insert_subreg a two-address instruction, vastly simplifying ↵Christopher Lamb2008-03-161-1/+8
| | | | | | LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48412 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace all target specific implicit def instructions with a target ↵Evan Cheng2008-03-151-1/+8
| | | | | | independent one: TargetInstrInfo::IMPLICIT_DEF. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
* SDIsel processes llvm.dbg.declare by recording the variable debug ↵Evan Cheng2008-02-021-0/+6
| | | | | | | | | | information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes. For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow ComplexExpressions in InstrInfo.td files to be slightly more... ↵Christopher Lamb2008-01-311-0/+12
| | | | | | | | | | | complex! ComplexExpressions can now have attributes which affect how TableGen interprets the pattern when generating matchin code. The first (and currently, only) attribute causes the immediate parent node of the ComplexPattern operand to be passed into the matching code rather than the node at the root of the entire DAG containing the pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46606 91177308-0d34-0410-b5e6-96231b3b80d8
* Start inferring side effect information more aggressively, and fix many bugs ↵Chris Lattner2008-01-101-0/+6
| | | | | | | | | | | | | | | in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45829 91177308-0d34-0410-b5e6-96231b3b80d8
* Split the impl of CodeGenInstruction out to its own .cpp file, add a ↵Chris Lattner2008-01-061-264/+2
| | | | | | getName() accessor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45645 91177308-0d34-0410-b5e6-96231b3b80d8
* change getQualifiedName to be a global function.Chris Lattner2008-01-051-0/+11
| | | | | | | | | Split the pattern parsing code out from the dag isel emitter into it's own file. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45632 91177308-0d34-0410-b5e6-96231b3b80d8
* remove attributions from utils.Chris Lattner2007-12-291-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45419 91177308-0d34-0410-b5e6-96231b3b80d8
* Add flags to indicate that there are "never" side effects or that there "may be"Bill Wendling2007-12-141-1/+7
| | | | | | | side effects for machine instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45022 91177308-0d34-0410-b5e6-96231b3b80d8
* Oops. Forgot these.Evan Cheng2007-12-131-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44969 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a flag for indirect branch instructions.Owen Anderson2007-11-121-0/+1
| | | | | | | Target maintainers: please check that the instructions for your target are correctly marked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44012 91177308-0d34-0410-b5e6-96231b3b80d8
* Add sqrt and powi intrinsics for long double.Dale Johannesen2007-09-281-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42423 91177308-0d34-0410-b5e6-96231b3b80d8
* Add CopyCost to TargetRegisterClass. This specifies the cost of copying a valueEvan Cheng2007-09-191-0/+1
| | | | | | | between two registers in the specific class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42123 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MVT::fAny for overloading intrinsics on floating-point types.Dan Gohman2007-08-161-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41128 91177308-0d34-0410-b5e6-96231b3b80d8
* This is the patch to provide clean intrinsic function overloading support in ↵Chandler Carruth2007-08-041-3/+2
| | | | | | | | | LLVM. It cleans up the intrinsic definitions and generally smooths the process for more complicated intrinsic writing. It will be used by the upcoming atomic intrinsics as well as vector and float intrinsics in the future. This also changes the syntax for llvm.bswap, llvm.part.set, llvm.part.select, and llvm.ct* intrinsics. They are automatically upgraded by both the LLVM ASM reader and the bitcode reader. The test cases have been updated, with special tests added to ensure the automatic upgrading is supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40807 91177308-0d34-0410-b5e6-96231b3b80d8
* Add target independent MachineInstr's to represent subreg insert/extract in ↵Christopher Lamb2007-07-261-1/+15
| | | | | | MBB's. PR1350 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40518 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach TableGen about the new vector types.Christopher Lamb2007-07-261-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40513 91177308-0d34-0410-b5e6-96231b3b80d8
* No need for noResults anymore.Evan Cheng2007-07-201-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40075 91177308-0d34-0410-b5e6-96231b3b80d8
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-1/+13
| | | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
* It's not necessary to do rounding for alloca operations when the requestedDan Gohman2007-07-181-0/+655
alignment is equal to the stack alignment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40004 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-11-15 09:28:21 +0000