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* Rename M_PREDICATED to M_PREDICABLE; opcode can be specified isPredicable ↵Evan Cheng2007-05-161-2/+2
| | | | | | without having a PredicateOperand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37116 91177308-0d34-0410-b5e6-96231b3b80d8
* For PR1297:Reid Spencer2007-04-011-3/+7
| | | | | | | | | | | Implement code generation for overloaded intrinsic functions. The basic difference is that "actual" argument types must be provided when constructing intrinsic names and types. Also, for recognition, only the prefix is examined. If it matches, the suffix is assumed to match. The suffix is checked by the Verifier, however. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35539 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the v1i64 type. This makes better code for this:Bill Wendling2007-03-261-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | #include <mmintrin.h> extern __m64 C; void baz(__v2si *A, __v2si *B) { *A = C; _mm_empty(); } We get this: _baz: call "L1$pb" "L1$pb": popl %eax movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax movq (%eax), %mm0 movl 4(%esp), %eax movq %mm0, (%eax) emms ret GCC gives us this: _baz: pushl %ebx call L3 "L00000000001$pb": L3: popl %ebx subl $8, %esp movl L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax movl (%eax), %edx movl 4(%eax), %ecx movl 16(%esp), %eax movl %edx, (%eax) movl %ecx, 4(%eax) emms addl $8, %esp popl %ebx ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35351 91177308-0d34-0410-b5e6-96231b3b80d8
* Recognize target instruction flag 'isReMaterializable'.Evan Cheng2007-03-191-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35159 91177308-0d34-0410-b5e6-96231b3b80d8
* reapplyChris Lattner2007-02-271-6/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34697 91177308-0d34-0410-b5e6-96231b3b80d8
* Backing outEvan Cheng2007-02-271-2/+6
| | | | | | | | | | | CodeGenTarget.cpp updated: 1.82 -> 1.83 Record.cpp updated: 1.55 -> 1.56 Record.h updated: 1.59 -> 1.60 TableGen.cpp updated: 1.47 -> 1.48 It's missing CallingConvEmitter.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34693 91177308-0d34-0410-b5e6-96231b3b80d8
* initial support for calling convention generation, still unfinished.Chris Lattner2007-02-271-6/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34682 91177308-0d34-0410-b5e6-96231b3b80d8
* Files missing from LABEL check in.Jim Laskey2007-01-261-1/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33539 91177308-0d34-0410-b5e6-96231b3b80d8
* What should be the last unnecessary <iostream>s in the library.Bill Wendling2006-12-071-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32333 91177308-0d34-0410-b5e6-96231b3b80d8
* Match TargetInstrInfo changes.Evan Cheng2006-12-011-3/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32107 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the isTwoAddress property from the CodeGenInstruction class. It shouldChris Lattner2006-11-151-1/+17
| | | | | | | | | | | not be used for anything other than backwards compat constraint handling. Add support for a new DisableEncoding property which contains a list of registers that should not be encoded by the generated code emitter. Convert the codeemitter generator to use this, fixing some PPC JIT regressions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31769 91177308-0d34-0410-b5e6-96231b3b80d8
* ADd support for adding constraints to suboperandsChris Lattner2006-11-151-29/+92
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31748 91177308-0d34-0410-b5e6-96231b3b80d8
* allow ptr_rc to explicitly appear in an instructions operand list, it doesn'tChris Lattner2006-11-101-1/+2
| | | | | | | have to be a subpart of a complex operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31618 91177308-0d34-0410-b5e6-96231b3b80d8
* emit TIED_TO correctlyChris Lattner2006-11-071-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31484 91177308-0d34-0410-b5e6-96231b3b80d8
* simplify the way operand flags and constraints are handled, making it easierChris Lattner2006-11-061-21/+30
| | | | | | | to extend. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31481 91177308-0d34-0410-b5e6-96231b3b80d8
* recognize ppc's blr instruction as predicatedChris Lattner2006-11-061-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31480 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up some code.Evan Cheng2006-11-041-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31451 91177308-0d34-0410-b5e6-96231b3b80d8
* eliminate need for the NumMIOperands field in Operand.Chris Lattner2006-11-031-1/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31432 91177308-0d34-0410-b5e6-96231b3b80d8
* Tied-to constraint must be op_with_larger_idx = op_with_smaller_idx or else ↵Evan Cheng2006-11-011-0/+3
| | | | | | throw an exception. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31361 91177308-0d34-0410-b5e6-96231b3b80d8
* Add operand constraints to TargetInstrInfo.Evan Cheng2006-11-011-0/+48
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31333 91177308-0d34-0410-b5e6-96231b3b80d8
* Added properties such as SDNPHasChain to ComplexPattern.Evan Cheng2006-10-111-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30890 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow more use of iPTR in patterns.Evan Cheng2006-06-151-22/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28790 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't generate getCalleeSaveReg and getCalleeSaveRegClasses anymore.Evan Cheng2006-05-181-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28376 91177308-0d34-0410-b5e6-96231b3b80d8
* TypoEvan Cheng2006-05-171-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28366 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove PointerType from target definition. Use abstract type MVT::iPTR toEvan Cheng2006-05-171-31/+27
| | | | | | | represent pointer type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28363 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow patterns to refer to physical registers that belong to multipleEvan Cheng2006-05-161-0/+17
| | | | | | | register classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28323 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo: Instr* -> Intr*Chris Lattner2006-04-101-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27568 91177308-0d34-0410-b5e6-96231b3b80d8
* Only compute intrinsic valuetypes when in a target .td file.Chris Lattner2006-03-281-2/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27197 91177308-0d34-0410-b5e6-96231b3b80d8
* revert this, it breaks things.Chris Lattner2006-03-281-4/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27196 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for decoding iPTR to the right pointer type.Chris Lattner2006-03-271-5/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27188 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure to initialize the TheDef field!Chris Lattner2006-03-241-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27078 91177308-0d34-0410-b5e6-96231b3b80d8
* Move CodeGenIntrinsic implementation to CodeGenTarget.cpp with the rest ofChris Lattner2006-03-241-0/+85
| | | | | | | | | the CodeGen* implementations. Parse the MVT::ValueType for each operand of the intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27075 91177308-0d34-0410-b5e6-96231b3b80d8
* getEnumName() missed v8i8, v4i16, and v2i32 typesEvan Cheng2006-03-191-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26869 91177308-0d34-0410-b5e6-96231b3b80d8
* New vector type v2f32.Evan Cheng2006-03-011-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26437 91177308-0d34-0410-b5e6-96231b3b80d8
* Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bitEvan Cheng2006-02-201-0/+3
| | | | | | | packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26294 91177308-0d34-0410-b5e6-96231b3b80d8
* PHI and INLINEASM are now builtin instructions provided by Target.tdChris Lattner2006-01-271-17/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25673 91177308-0d34-0410-b5e6-96231b3b80d8
* * Remove instruction fields hasInFlag / hasOutFlag and added SNDPInFlag andEvan Cheng2006-01-091-2/+0
| | | | | | | | | | SNDPOutFlag to DAG nodes. These properties do not belong to target specific instructions. * Added DAG node property SNDPOptInFlag. It's same as SNDPInFlag except it's optional. Used by ret / call, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25154 91177308-0d34-0410-b5e6-96231b3b80d8
* Added field noResults to Instruction.Evan Cheng2005-12-261-0/+1
| | | | | | | | | | | | | Currently tblgen cannot tell which operands in the operand list are results so it assumes the first one is a result. This is bad. Ideally we would fix this by separating results from inputs, e.g. (res R32:$dst), (ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding 'let noResults = 1' is the workaround to tell tblgen that the instruction does not produces a result. It works for now since tblgen does not support instructions which produce multiple results. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25017 91177308-0d34-0410-b5e6-96231b3b80d8
* * Support for hasInFlag and hasOutFlag (on instructions). Remove nameless FLAGEvan Cheng2005-12-231-0/+2
| | | | | | | | support which is fragile. * Fixed a number of bugs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24996 91177308-0d34-0410-b5e6-96231b3b80d8
* Support for read / write from explicit registers with FlagVT type.Evan Cheng2005-12-171-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24753 91177308-0d34-0410-b5e6-96231b3b80d8
* * Added an explicit type field to ComplexPattern.Evan Cheng2005-12-081-3/+5
| | | | | | | * Renamed MatchingNodes to RootNodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24636 91177308-0d34-0410-b5e6-96231b3b80d8
* Added support for ComplexPattern. These are patterns that require C++ patternEvan Cheng2005-12-081-0/+9
| | | | | | | | matching code that is not currently auto-generated by tblgen, e.g. X86 addressing mode. Selection routines for complex patterns can return multiple operands, e.g. X86 addressing mode returns 4. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24634 91177308-0d34-0410-b5e6-96231b3b80d8
* * Commit the fix (by Chris) for a tblgen type inferencing bug.Evan Cheng2005-12-041-0/+1
| | | | | | | | | | | | * Enhanced tblgen to handle instructions which have chain operand and writes a chain result. * Enhanced tblgen to handle instructions which produces no results. Part of the change is a temporary hack which relies on instruction property (e.g. isReturn, isBranch). The proper fix would be to change the .td syntax to separate results dag from ops dag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24587 91177308-0d34-0410-b5e6-96231b3b80d8
* Support multiple ValueTypes per RegisterClass, needed for upcoming vectorNate Begeman2005-12-011-8/+20
| | | | | | | work. This change has no effect on generated code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24563 91177308-0d34-0410-b5e6-96231b3b80d8
* Nuke CodeGenInstruction's ValueType member, it is no longer used.Nate Begeman2005-12-011-9/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24556 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the new vector types to tablegenNate Begeman2005-11-291-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24514 91177308-0d34-0410-b5e6-96231b3b80d8
* Initialize this variable on all paths, fixing a crasher in windows. ThanksChris Lattner2005-11-191-1/+1
| | | | | | | to JeffC for pointing this out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24426 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach tblgen about instruction operands that have multiple MachineInstrChris Lattner2005-11-191-1/+4
| | | | | | | | operands, digging into them to find register values (used on X86). Patch by Evan Cheng! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24424 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename Record::getValueAsListDef to getValueAsListOfDefs, to more accuratelyChris Lattner2005-10-281-20/+8
| | | | | | | | reflect what it is. Convert some more code over to use it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24072 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not let getLegalValueTypes return a list with duplicates in itChris Lattner2005-10-141-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23723 91177308-0d34-0410-b5e6-96231b3b80d8
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