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* Make the register enum value part of the CodeGenRegister struct.Jim Grosbach2011-03-111-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127448 91177308-0d34-0410-b5e6-96231b3b80d8
* Trailing whitespace.Jim Grosbach2011-03-111-20/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127447 91177308-0d34-0410-b5e6-96231b3b80d8
* Flag -> Glue, the ongoing sagaChris Lattner2010-12-231-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122513 91177308-0d34-0410-b5e6-96231b3b80d8
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-211-1/+1
| | | | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122310 91177308-0d34-0410-b5e6-96231b3b80d8
* various cleanups to tblgen, patch by Garrison Venn!Chris Lattner2010-12-151-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121837 91177308-0d34-0410-b5e6-96231b3b80d8
* eliminate the Records global variable, patch by Garrison Venn!Chris Lattner2010-12-131-3/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121659 91177308-0d34-0410-b5e6-96231b3b80d8
* a bunch of random cleanup, move a helper to CGT where it belongs.Chris Lattner2010-11-021-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118031 91177308-0d34-0410-b5e6-96231b3b80d8
* eliminate the old InstFormatName which is always "AsmString",Chris Lattner2010-11-011-7/+2
| | | | | | | simplify CodeGenInstruction. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117891 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a long standing wart: all the ComplexPattern's were beingChris Lattner2010-09-211-0/+4
| | | | | | | | | | | | passed the root of the match, even though only a few patterns actually needed this (one in X86, several in ARM [which should be refactored anyway], and some in CellSPU that I don't feel like detangling). Instead of requiring all ComplexPatterns to take the dead root, have targets opt into getting the root by putting SDNPWantRoot on the ComplexPattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an MVT::x86mmx type. It will take the place of all current MMX vector types.Bill Wendling2010-09-071-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113261 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix whitespace, because I'm OCD.Bill Wendling2010-09-071-38/+38
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113250 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove IntrWriteMem, as it's the default. Rename IntrWriteArgMemDan Gohman2010-08-051-5/+3
| | | | | | | to IntrReadWriteArgMem, as it's for reading as well as writing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110395 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling2010-07-161-1/+1
| | | | | | | thus is a much more meaningful name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new target independent COPY instruction and code to lower it.Jakob Stoklund Olesen2010-07-021-0/+1
| | | | | | | | | | | The COPY instruction is intended to replace the target specific copy instructions for virtual registers as well as the EXTRACT_SUBREG and INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection DAG. COPY is lowered to native register copies by LowerSubregs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107529 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up TargetOpcodes.h a bit, and limit the number of places where the fullJakob Stoklund Olesen2010-07-021-48/+28
| | | | | | | | | list of predefined instructions appear. Add some consistency checks. Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it is hardly worth the effort. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107520 91177308-0d34-0410-b5e6-96231b3b80d8
* Add StringRef::compare_numeric and use it to sort TableGen register records.Jakob Stoklund Olesen2010-05-261-0/+2
| | | | | | | This means that our Registers are now ordered R7, R8, R9, R10, R12, ... Not R1, R10, R11, R12, R2, R3, ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104745 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen2010-05-241-11/+28
| | | | | | | | | | | structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding a v8i64 512-bit vector type. This will be used to model ARM NEON ↵Evan Cheng2010-05-131-0/+1
| | | | | | intrinsics which translate into a pair of vld / vst instructions that can load / store 8 consecutive 64-bit (D) registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103746 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a pseudo instruction REG_SEQUENCE that takes a list of registers andEvan Cheng2010-05-011-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sub-register indices and outputs a single super register which is formed from a consecutive sequence of registers. This is used as register allocation / coalescing aid and it is useful to represent instructions that output register pairs / quads. For example, v1024, v1025 = vload <address> where v1024 and v1025 forms a register pair. This really should be modelled as v1024<3>, v1025<4> = vload <address> but it would violate SSA property before register allocation is done. Currently we use insert_subreg to form the super register: v1026 = implicit_def v1027 - insert_subreg v1026, v1024, 3 v1028 = insert_subreg v1027, v1025, 4 ... = use v1024 = use v1028 But this adds pseudo live interval overlap between v1024 and v1025. We can now modeled it as v1024, v1025 = vload <address> v1026 = REG_SEQUENCE v1024, 3, v1025, 4 ... = use v1024 = use v1026 After coalescing, it will be v1026<3>, v1025<4> = vload <address> ... = use v1026<3> = use v1026 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102815 91177308-0d34-0410-b5e6-96231b3b80d8
* fix CodeGenTarget::getRegisterVTs to not return the Chris Lattner2010-03-271-0/+5
| | | | | | | | | same vt multiple times for a register. For example, ECX is in 5 different i32 reg classes, just return 1 i32 instead of 5. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99727 91177308-0d34-0410-b5e6-96231b3b80d8
* reject void in intrinsic type lists.Chris Lattner2010-03-231-7/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99347 91177308-0d34-0410-b5e6-96231b3b80d8
* Change intrinsic result type for void to store it as an empty listChris Lattner2010-03-221-3/+6
| | | | | | | | instead of as a single element list with VoidTy. Now with a fix for the verifier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99206 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r99009 temporarily it seems to be breaking the bots.Eric Christopher2010-03-191-6/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99011 91177308-0d34-0410-b5e6-96231b3b80d8
* Change intrinsic result type for void to store it as an empty listChris Lattner2010-03-191-3/+6
| | | | | | | instead of as a single element list with VoidTy. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99009 91177308-0d34-0410-b5e6-96231b3b80d8
* add a new SDNPVariadic SDNP node flag, and use it inChris Lattner2010-03-191-0/+2
| | | | | | | | | dag isel gen instead of instruction properties. This allows the oh-so-useful behavior of matching a variadic non-root node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98934 91177308-0d34-0410-b5e6-96231b3b80d8
* Finally change the instruction looking map to be a densemap fromChris Lattner2010-03-191-16/+29
| | | | | | | | | | record* -> instrinfo instead of std::string -> instrinfo. This speeds up tblgen on cellcpu from 7.28 -> 5.98s with a debug build (20%). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98916 91177308-0d34-0410-b5e6-96231b3b80d8
* make inst_begin/inst_end iterate over InstructionsByEnumValue.Chris Lattner2010-03-191-23/+24
| | | | | | | Use CodeGenTarget::getInstNamespace in one place and fix it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98915 91177308-0d34-0410-b5e6-96231b3b80d8
* revert 98912Chris Lattner2010-03-191-15/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98914 91177308-0d34-0410-b5e6-96231b3b80d8
* make inst_begin/inst_end iterate over InstructionsByEnumValue.Chris Lattner2010-03-191-15/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98912 91177308-0d34-0410-b5e6-96231b3b80d8
* change Target.getInstructionsByEnumValue to return a referenceChris Lattner2010-03-191-17/+14
| | | | | | | | to a vector that CGT stores instead of synthesizing it on every call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98910 91177308-0d34-0410-b5e6-96231b3b80d8
* factor copy and paste code.Chris Lattner2010-03-191-53/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98908 91177308-0d34-0410-b5e6-96231b3b80d8
* look up instructions by record, not by name.Chris Lattner2010-03-191-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98904 91177308-0d34-0410-b5e6-96231b3b80d8
* Completely rewrite tblgen's type inference mechanism,Chris Lattner2010-03-151-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | changing the primary datastructure from being a "std::vector<unsigned char>" to being a new TypeSet class that actually has (gasp) invariants! This changes more things than I remember, but one major innovation here is that it enforces that named input values agree in type with their output values. This also eliminates code that transparently assumes (in some cases) that SDNodeXForm input/output types are the same, because this is wrong in many case. This also eliminates a bug which caused a lot of ambiguous patterns to go undetected, where a register class would sometimes pick the first possible type, causing an ambiguous pattern to get arbitrary results. With all the recent target changes, this causes no functionality change! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98534 91177308-0d34-0410-b5e6-96231b3b80d8
* move target-independent opcodes out of TargetInstrInfoChris Lattner2010-02-091-5/+5
| | | | | | | | | | into TargetOpcodes.h. #include the new TargetOpcodes.h into MachineInstr. Add new inline accessors (like isPHI()) to MachineInstr, and start using them throughout the codebase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95687 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove DEBUG_DECLARE, looks like we don't need it.Dale Johannesen2010-01-151-8/+1
| | | | | | | | Also, DEBUG_VALUE has side effects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93498 91177308-0d34-0410-b5e6-96231b3b80d8
* Add DEBUG_DECLARE. Not used yet.Dale Johannesen2010-01-091-1/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93040 91177308-0d34-0410-b5e6-96231b3b80d8
* Add DEBUG_VALUE. Not used yet.Dale Johannesen2010-01-081-1/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93030 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the CPAttrParentAsRoot code, which is unused, and inconvenientDan Gohman2010-01-041-12/+0
| | | | | | | for a refactoring I'm working on. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92503 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce the TargetInstrInfo::KILL machine instruction and get rid of theJakob Stoklund Olesen2009-09-281-5/+5
| | | | | | | | | | unused DECLARE instruction. KILL is not yet used anywhere, it will replace TargetInstrInfo::IMPLICIT_DEF in the places where IMPLICIT_DEF is just used to alter liveness of physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83006 91177308-0d34-0410-b5e6-96231b3b80d8
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-54/+54
| | | | | | | | | while the latter is capable of representing either a primitive or an extended type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a few more places in TableGen that need to handle EVT::vAny types.Bob Wilson2009-08-111-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78643 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new overloaded EVT::vAny type for use in TableGen to allow intrinsicBob Wilson2009-08-111-2/+3
| | | | | | | arguments that are vectors of any size and element type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78631 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-56/+56
| | | | | | own struct type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
* Match X86 register names to number.Daniel Dunbar2009-07-291-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77404 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the v3i32 and v3f32 value types: they are notDuncan Sands2009-07-151-2/+0
| | | | | | | native for any supported targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75785 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 75308.Bob Wilson2009-07-141-17/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75565 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new vector types for 192-bit, 348-bit and 512-bit sizes.Bob Wilson2009-07-101-2/+17
| | | | | | | | These are needed to represent ARM Neon struct datatypes containing 2, 3 or 4 separate vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75308 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor TableGen's llvm::getName to share code with llvm::getEnumName,Bob Wilson2009-07-101-41/+4
| | | | | | | since names are the same for almost all the types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75302 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new ValueType for metadata.Devang Patel2009-07-061-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74882 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace std::iostreams with raw_ostream in TableGen.Daniel Dunbar2009-07-031-5/+4
| | | | | | | | | - Sorry, I can't help myself. - No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74742 91177308-0d34-0410-b5e6-96231b3b80d8
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