aboutsummaryrefslogtreecommitdiffstats
path: root/utils/TableGen/FastISelEmitter.cpp
Commit message (Collapse)AuthorAgeFilesLines
* factor the operand list (and related fields/operations) out of Chris Lattner2010-11-011-2/+2
| | | | | | | CodeGenInstruction into its own helper class. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117893 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow strict subclasses of register classes, this way we can handleEric Christopher2010-08-251-2/+3
| | | | | | | | | | | ARM instructions with: foo GPR, rGPR which happens a lot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112025 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment.Eric Christopher2010-08-241-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111996 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove predicate workaround, we're going to require that predicateEric Christopher2010-08-171-9/+0
| | | | | | | and optional def operands are handled in the backend support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111220 91177308-0d34-0410-b5e6-96231b3b80d8
* Filter out patterns that have PredicateOperands.Eric Christopher2010-07-281-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109572 91177308-0d34-0410-b5e6-96231b3b80d8
* 80-col.Eric Christopher2010-07-261-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109407 91177308-0d34-0410-b5e6-96231b3b80d8
* Hack around extracts that aren't easy to process.Eric Christopher2010-07-211-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109043 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace copyRegToReg with COPY in FastISelEmitter.Jakob Stoklund Olesen2010-07-111-13/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108071 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman2010-07-101-2/+2
| | | | | | | | | | - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
* --- Reverse-merging r107947 into '.':Bob Wilson2010-07-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
* These changes should have accompanied r107943.Dan Gohman2010-07-091-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107947 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 107840 107839 107813 107804 107800 107797 107791.Dan Gohman2010-07-081-2/+2
| | | | | | | Debug info intrinsics win for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8
* Give FunctionLoweringInfo an MBB member, avoiding the need to pass itDan Gohman2010-07-071-2/+2
| | | | | | | | | around everywhere, and also give it an InsertPt member, to enable isel to operate at an arbitrary position within a block, rather than just appending to a block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107791 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor code simplification.Dan Gohman2010-05-271-9/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104845 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the SubRegIndex TableGen class.Jakob Stoklund Olesen2010-05-241-8/+11
| | | | | | | This is the beginning of purely symbolic subregister indices, but we need a bit of jiggling before the explicit numeric indices can be completely removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104492 91177308-0d34-0410-b5e6-96231b3b80d8
* Add initial kill flag support to FastISel.Dan Gohman2010-05-111-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103529 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-2/+2
| | | | | | | doesn't have to guess. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
* add plumbing for handling multiple result nodes Chris Lattner2010-03-241-1/+3
| | | | | | | in some more places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99366 91177308-0d34-0410-b5e6-96231b3b80d8
* major surgery on tblgen: generalize TreePatternNodeChris Lattner2010-03-191-7/+14
| | | | | | | | | | to maintain a list of types (one for each result of the node) instead of a single type. There are liberal hacks added to emulate the old behavior in various situations, but they can start disolving now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98999 91177308-0d34-0410-b5e6-96231b3b80d8
* look up instructions by record, not by name.Chris Lattner2010-03-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98904 91177308-0d34-0410-b5e6-96231b3b80d8
* Completely rewrite tblgen's type inference mechanism,Chris Lattner2010-03-151-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | changing the primary datastructure from being a "std::vector<unsigned char>" to being a new TypeSet class that actually has (gasp) invariants! This changes more things than I remember, but one major innovation here is that it enforces that named input values agree in type with their output values. This also eliminates code that transparently assumes (in some cases) that SDNodeXForm input/output types are the same, because this is wrong in many case. This also eliminates a bug which caused a lot of ambiguous patterns to go undetected, where a register class would sometimes pick the first possible type, causing an ambiguous pattern to get arbitrary results. With all the recent target changes, this causes no functionality change! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98534 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use the ISD::NodeType enum for SDNode opcodes, as CodeGenDan Gohman2010-01-051-1/+1
| | | | | | | | uses several kinds of opcode values which are not declared within that enum. This fixes PR5946. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92794 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some unused variables and methods warned about byDuncan Sands2009-09-061-1/+0
| | | | | | | icc (#177, partial). Patch by Erick Tryzelaar. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81106 91177308-0d34-0410-b5e6-96231b3b80d8
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-16/+16
| | | | | | | | | while the latter is capable of representing either a primitive or an extended type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-13/+13
| | | | | | own struct type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace std::iostreams with raw_ostream in TableGen.Daniel Dunbar2009-07-031-10/+9
| | | | | | | | | - Sorry, I can't help myself. - No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74742 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen for fast isel seems to assume an 'imm'Dale Johannesen2009-05-211-2/+2
| | | | | | | | | | operand is the last in a pattern. There is no reason this should be true (although apparently it always is right now). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72232 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and ↵Evan Cheng2009-01-221-2/+3
| | | | | | SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62762 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for having multiple predicates on a TreePatternNode.Dan Gohman2008-10-151-2/+2
| | | | | | | | | This will allow predicates to be composed, which will allow the predicate definitions to become less redundant, and eventually will allow DAGISelEmitter.cpp to emit less redundant code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57562 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the primary fast-isel top-level comments to FastISel.cpp, whereDan Gohman2008-09-301-24/+6
| | | | | | | they'll be a little more visible. Also, update and reword them a bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56877 91177308-0d34-0410-b5e6-96231b3b80d8
* Correctly handle physical register inputs. They are not explicit input ↵Evan Cheng2008-09-081-9/+30
| | | | | | operands in the resulting machine instrs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55893 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix indentation of generated code.Evan Cheng2008-09-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55876 91177308-0d34-0410-b5e6-96231b3b80d8
* Ignore multi-instruction patterns. e.g.Evan Cheng2008-09-071-0/+14
| | | | | | | | def : Pat<(i8 (trunc GR32:$src)), (i8 (EXTRACT_SUBREG (MOV32to32_ GR32:$src), x86_subreg_8bit))> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55875 91177308-0d34-0410-b5e6-96231b3b80d8
* Let tblgen only generate fastisel routines, not the class definition. This ↵Evan Cheng2008-09-031-106/+5
| | | | | | makes it easier for targets to define its own fastisel class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55679 91177308-0d34-0410-b5e6-96231b3b80d8
* Add initial support for fast isel of instructions that have inputs pinned to ↵Owen Anderson2008-08-291-19/+107
| | | | | | physical registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55545 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a target callback for FastISel.Dan Gohman2008-08-281-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55512 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for fast-isel of opcodes that require use of extract_subreg. ↵Owen Anderson2008-08-281-21/+43
| | | | | | Because of how extract_subreg is treated, it requires special case handling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55480 91177308-0d34-0410-b5e6-96231b3b80d8
* Update a comment to reflect recent changes.Dan Gohman2008-08-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55418 91177308-0d34-0410-b5e6-96231b3b80d8
* Basic FastISel support for floating-point constants.Dan Gohman2008-08-271-0/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55401 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor a bunch of FastISelEmitter code into a helper class, andDan Gohman2008-08-261-27/+63
| | | | | | | | put each major step in a separate function. This makes the high level sequence of events easier to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55385 91177308-0d34-0410-b5e6-96231b3b80d8
* We need to check that the return type is correct, even in cases where we don'tOwen Anderson2008-08-261-0/+3
| | | | | | | have a return type that differs from the operand types. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55376 91177308-0d34-0410-b5e6-96231b3b80d8
* Throw the switch to allow FastISel to emit instructions whose return types ↵Owen Anderson2008-08-261-9/+16
| | | | | | different from their inputs. Next step: adding lowering pattens in FastISel that actually use these newly available opcodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55349 91177308-0d34-0410-b5e6-96231b3b80d8
* Enhance TableGen to emit code for FastISel of opcodes with variadic return ↵Owen Anderson2008-08-261-13/+97
| | | | | | types without slowing down opcodes that are not variadic. No such opcodes are currently generated, but in theory it should be a matter of just hitting the switch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55347 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a RetVT parameter to emitted FastISel methods, so that we will be able ↵Owen Anderson2008-08-251-8/+14
| | | | | | | | | to pass the desired return type down. This is not currently used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55345 91177308-0d34-0410-b5e6-96231b3b80d8
* Deepen the map structure tablegen uses to compute FastISel patterns, in ↵Owen Anderson2008-08-251-54/+61
| | | | | | | | | preparation for having patterns with return types that differ from their input types. This is not yet used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55344 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for fast isel of (integer) immediate materialization pattens, ↵Owen Anderson2008-08-251-3/+6
| | | | | | | | | and use them to support bitcast of constants in fast isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55325 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a few comments.Dan Gohman2008-08-221-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55157 91177308-0d34-0410-b5e6-96231b3b80d8
* Factor out the predicate check code from DAGISelEmitter.cppDan Gohman2008-08-221-28/+66
| | | | | | | | | | and use it in FastISelEmitter.cpp, and make FastISel subtarget aware. Among other things, this lets it work properly on x86 targets that don't have SSE, where it successfully selects x87 instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55156 91177308-0d34-0410-b5e6-96231b3b80d8
* Basic fast-isel support for instructions with constant int operands.Dan Gohman2008-08-211-13/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55099 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the code that limited FastISel to certain fixed signatures.Dan Gohman2008-08-211-19/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55096 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2024-10-28 05:26:12 +0000