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* pr9367: Add missing predicated BLX instructions.Bob Wilson2011-03-031-1/+1
| | | | | | Patch by Jyun-Yan You, with some minor adjustments and a testcase from me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126915 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the clang attribute emitter about InheritableParamAttr.John McCall2011-03-021-2/+16
| | | | | | | | Intended to be atomic with clang r126828. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126827 91177308-0d34-0410-b5e6-96231b3b80d8
* trailing whitespace.Jim Grosbach2011-03-012-92/+92
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126733 91177308-0d34-0410-b5e6-96231b3b80d8
* Generalize the register matching code in DAGISel a bit.Jim Grosbach2011-03-013-21/+45
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126731 91177308-0d34-0410-b5e6-96231b3b80d8
* Narrow right shifts need to encode their immediates differently from a normalBill Wendling2011-03-011-0/+3
| | | | | | | | | | | shift. 16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0> 32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0> 64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
* A new TableGen feature! (Not turned on just yet.)Bill Wendling2011-02-262-0/+250
| | | | | | | | | | | | | | | | | | | | | InstAlias<{alias}, {aliasee}>; The InstAlias instruction should be able to go from the MCInst to the {alias}. All of the information is there to match the MCInst with the {aliasee}. From there, it's a simple matter to emit the {alias}, with the correct operands from the {aliasee}. The code this patch generates can be used by the InstPrinter to automatically print out the alias without having to write special C++ code to handle the situation. This is a WIP, and therefore are several limitations. For instance, it cannot handle AsmOperands at the moment. It also doesn't know what to do when two {alias}es match the same {aliasee}. (Currently, it just ignores those two cases and allows the printInstruction method to handle them.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126538 91177308-0d34-0410-b5e6-96231b3b80d8
* In utils/TableGen/ClangSACheckersEmitter.cpp, set the 'Hidden' bit for checkers.Argyrios Kyrtzidis2011-02-241-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126436 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement xgetbv and xsetbv.Rafael Espindola2011-02-221-1/+3
| | | | | | Patch by Jai Menon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126165 91177308-0d34-0410-b5e6-96231b3b80d8
* Put targets on folders, if the IDE supports the feature.Oscar Fuentes2011-02-201-1/+1
| | | | | | Requires CMake 2.8.3 or newer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126092 91177308-0d34-0410-b5e6-96231b3b80d8
* CMake: updated list of tblgen source files.Oscar Fuentes2011-02-181-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125969 91177308-0d34-0410-b5e6-96231b3b80d8
* Add FixedLenDecoderEmitter, the skeleton of a new disassembler emitter for ↵Owen Anderson2011-02-184-98/+1532
| | | | | | | | | | | | | | fixed-length instruction encodings. A major part of its (eventual) goal is to support a much cleaner separation between disassembly callbacks provided by the target and the disassembler emitter itself, i.e. not requiring hardcoding of knowledge in tblgen like the existing disassembly emitters do. The hope is that some day this will allow us to replace the existing non-Thumb ARM disassembler and remove some of the hacks the old one introduced to tblgen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125966 91177308-0d34-0410-b5e6-96231b3b80d8
* Check that MnemonicAlias doesn't map back to the same string.Joerg Sonnenberger2011-02-171-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125792 91177308-0d34-0410-b5e6-96231b3b80d8
* Add serialization for Expr* arguments for attributes to clang tablegen files.Sean Hunt2011-02-171-0/+2
| | | | | | Patch thanks to Zach Anderson. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125721 91177308-0d34-0410-b5e6-96231b3b80d8
* When tablegen'ing the clang analyzer checkers:Argyrios Kyrtzidis2011-02-151-27/+62
| | | | | | | | -Use the tablegen class name for the checker class name. -Mark checker packages as hidden/not hidden. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125558 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the ClangSACheckersEmitter tablegen backend which will be used for the ↵Argyrios Kyrtzidis2011-02-144-0/+233
| | | | | | clang static analyzer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125493 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix encoding and add parsing support for the arm/thumb CPS instruction:Bruno Cardoso Lopes2011-02-141-0/+2
| | | | | | | | | | | | | | - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125489 91177308-0d34-0410-b5e6-96231b3b80d8
* Wrap the struct in an anonymous namespace.Argyrios Kyrtzidis2011-02-131-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125452 91177308-0d34-0410-b5e6-96231b3b80d8
* AsmMatcher custom operand parser failure enhancements.Jim Grosbach2011-02-121-17/+19
| | | | | | | | | | | | | Teach the AsmMatcher handling to distinguish between an error custom-parsing an operand and a failure to match. The former should propogate the error upwards, while the latter should continue attempting to parse with alternative matchers. Update the ARM asm parser accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125426 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy out asm matcher .inc output.Jim Grosbach2011-02-111-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125408 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't return before calling the post-processing function(s).Bill Wendling2011-02-101-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125256 91177308-0d34-0410-b5e6-96231b3b80d8
* Do AsmMatcher operand classification per-opcode.Jim Grosbach2011-02-101-88/+29
| | | | | | | | | | | | When matching operands for a candidate opcode match in the auto-generated AsmMatcher, check each operand against the expected operand match class. Previously, operands were classified independently of the opcode being handled, which led to difficulties when operand match classes were more complicated than simple subclass relationships. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125245 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement support for custom target specific asm parsing of operands.Bruno Cardoso Lopes2011-02-071-3/+262
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Motivation: Improve the parsing of not usual (different from registers or immediates) operand forms. This commit implements only the generic support. The ARM specific modifications will come next. A table like the one below is autogenerated for every instruction containing a 'ParserMethod' in its AsmOperandClass static const OperandMatchEntry OperandMatchTable[20] = { /* Mnemonic, Operand List Mask, Operand Class, Features */ { "cdp", 29 /* 0, 2, 3, 4 */, MCK_Coproc, Feature_IsThumb|Feature_HasV6 }, { "cdp", 58 /* 1, 3, 4, 5 */, MCK_Coproc, Feature_IsARM }, A matcher function very similar (but lot more naive) to MatchInstructionImpl scans the table. After the mnemonic match, the features are checked and if the "to be parsed" operand index is present in the mask, there's a real match. Then, a switch like the one below dispatch the parsing to the custom method provided in 'ParseMethod': case MCK_Coproc: return TryParseCoprocessorOperandName(Operands); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125030 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/AsmMatcher: Sink ConvertToMCInst into the TargetAsmParser instance, whichDaniel Dunbar2011-02-041-3/+8
| | | | | | implicitly allows custom conversions to be member functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124908 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.Jason W Kim2011-02-041-0/+7
| | | | | | | | | | | | | | | | | | | (yes, this is different from R_ARM_CALL) - Adds a new method getARMBranchTargetOpValue() which handles the necessary distinction between the conditional and unconditional br/bl needed for ARM/ELF At least for ARM mode, the needed fixup for conditional versus unconditional br/bl is identical, but the ARM docs and existing ARM tools expect this reloc type... Added a few FIXME's for future naming fixups in ARMInstrInfo.td git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124895 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/AsmParser: Add support for allowing the conversion process to fail (viaDaniel Dunbar2011-02-041-8/+17
| | | | | | custom conversion functions). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124872 91177308-0d34-0410-b5e6-96231b3b80d8
* MC/AsmMatcher: Add support for custom conversion functions.Daniel Dunbar2011-02-041-1/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124870 91177308-0d34-0410-b5e6-96231b3b80d8
* Silence uninitialized value warnings.David Greene2011-02-041-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124869 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up a bit.Jim Grosbach2011-02-031-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124832 91177308-0d34-0410-b5e6-96231b3b80d8
* Changes for building Clang and others using LLVM as an externalOscar Fuentes2011-02-031-0/+4
| | | | | | | | | | | | | library. Installs tblgen (required by Clang). Translates handling of user settings and platform-dependant options to its own file, where it can included by another project. Installs the .cmake files required by projects like Clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124816 91177308-0d34-0410-b5e6-96231b3b80d8
* Changed the TableGen created MatchInstructionImpl() setting of ErrorInfo.Kevin Enderby2011-02-021-3/+1
| | | | | | | | | | | | The algorithm for identifying which operand is invalid will now always point to some operand and not the mnemonic sometimes. The change is now that ErrorInfo is the index of the highest operand that does not match for any of the matching mnemonics records. And no longer the ~0U value when the mnemonic matches and not every record with a matching mnemonic has the same mismatching operand index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124734 91177308-0d34-0410-b5e6-96231b3b80d8
* [AVX] Implement EnforceSmallerThan for mixed int/fp type lists. ThisDavid Greene2011-02-011-27/+130
| | | | | | | | | | | | | | makes type checking for extract_subvector and insert_subvector more robust and will allow stricter typechecking of more patterns in the future. This change handles int and fp as disjoint sets so that it will enforce integer types to be smaller than the largest integer type and fp types to be smaller than the largest fp type. There is no attempt to check type sizes across the int/fp sets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124672 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a comment typo.Bob Wilson2011-01-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124450 91177308-0d34-0410-b5e6-96231b3b80d8
* Clang: separate the access-control diagnostics from other diagnostics that ↵Douglas Gregor2011-01-271-1/+7
| | | | | | do not have SFINAE behavior. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124440 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a MnemonicIsValid method to the asm matcher.Bob Wilson2011-01-261-0/+11
| | | | | | Patch by Bill Wendling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124328 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix spelling of CouldMatchAmbiguouslyWith method name.Bob Wilson2011-01-261-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124324 91177308-0d34-0410-b5e6-96231b3b80d8
* Whitespace and 80-column fixes.Bob Wilson2011-01-261-119/+109
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124323 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve the AsmMatcher's ability to handle suboperands.Bob Wilson2011-01-263-172/+247
| | | | | | | | | | | | | | | When an operand class is defined with MIOperandInfo set to a list of suboperands, the AsmMatcher has so far required that operand to also define a custom ParserMatchClass, and InstAlias patterns have not been able to set the individual suboperands separately. This patch removes both of those restrictions. If a "compound" operand does not override the default ParserMatchClass, then the AsmMatcher will now parse its suboperands separately. If an InstAlias operand has the same class as the corresponding compound operand, then it will be handled as before; but if that check fails, TableGen will now try to match up a sequence of InstAlias operands with the corresponding suboperands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124314 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: PointerLikeRegClass can be accepted to operand.NAKAMURA Takumi2011-01-262-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124271 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix whitespace.NAKAMURA Takumi2011-01-261-58/+58
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124270 91177308-0d34-0410-b5e6-96231b3b80d8
* tblgen/AsmMatcherEmitter: Fix alias handling to honor -match-prefix.Daniel Dunbar2011-01-241-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124154 91177308-0d34-0410-b5e6-96231b3b80d8
* [AVX] Add type checking support for vector/subvector type constraints.David Greene2011-01-242-1/+54
| | | | | | | | | | This will be used to check patterns referencing a forthcoming INSERT_SUBVECTOR SDNode. INSERT_SUBVECTOR in turn is very useful for matching to VINSERTF128 instructions and complements the already existing EXTRACT_SUBVECTOR SDNode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124145 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM uses '.' in their tokens. Give it a name instead of a numeric value.Bill Wendling2011-01-221-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124026 91177308-0d34-0410-b5e6-96231b3b80d8
* tblgen: Add support for non-inheritable attributesPeter Collingbourne2011-01-211-12/+47
| | | | | | | This patch makes the necessary changes to TableGen to support non-inheritable attributes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123958 91177308-0d34-0410-b5e6-96231b3b80d8
* Move InstAlias check of argument types to a separate loop.Bob Wilson2011-01-201-11/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123934 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy comment.Bob Wilson2011-01-201-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123933 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix broken check for InstAlias argument used with different types.Bob Wilson2011-01-201-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123932 91177308-0d34-0410-b5e6-96231b3b80d8
* Precompute InstAlias operand mapping to result instruction operand indices.Bob Wilson2011-01-203-24/+9
| | | | | | | There should be no functional change from this, but I think it's simpler this way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123931 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment for gen-clang-decl-nodes tblgen backend, from Michael HanDouglas Gregor2011-01-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123833 91177308-0d34-0410-b5e6-96231b3b80d8
* When matching asm operands, always try to match the most restricted type first.Owen Anderson2011-01-181-3/+36
| | | | | | | | | | | | | Unfortunately, while this is the "right" thing to do, it breaks some ARM asm parsing tests because MemMode5 and ThumbMemModeReg are ambiguous. This is tricky to resolve since neither is a subset of the other. XFAIL the test for now. The old way was broken in other ways, just ways we didn't happen to be testing, and our ARM asm parsing is going to require significant revisiting at a later point anyways. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123786 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for parsing and encoding ARM's official syntax for the BFI ↵Bruno Cardoso Lopes2011-01-182-0/+6
| | | | | | instruction git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123770 91177308-0d34-0410-b5e6-96231b3b80d8
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