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* Add support for a new Apple-style build target, EmbeddedSim, that buildsBob Wilson2010-07-202-5/+20
| | | | | | | llvmCore for the iOS Simulator. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108922 91177308-0d34-0410-b5e6-96231b3b80d8
* remove option from tablegen for building static header.Chris Lattner2010-07-203-27/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108893 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!Bruno Cardoso Lopes2010-07-191-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108769 91177308-0d34-0410-b5e6-96231b3b80d8
* Save a copy of the unstripped libLTO.dylib in $SYM_DIR. Clean up the codeBob Wilson2010-07-191-9/+11
| | | | | | | | for dealing with libLTO.dylib to put it all in one place and to allow use of DISABLE_USR_LINKS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108753 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove code duplication.Mikhail Glushenkov2010-07-191-26/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108718 91177308-0d34-0410-b5e6-96231b3b80d8
* Better error reporting for switch_list.Mikhail Glushenkov2010-07-191-9/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108714 91177308-0d34-0410-b5e6-96231b3b80d8
* TblGen/AsmMatcher: Add support for honoring instruction Requires<[]> ↵Daniel Dunbar2010-07-191-2/+136
| | | | | | | | attributes as part of the matcher. - Currently includes a hack to limit ourselves to "In32BitMode" and "In64BitMode", because we don't have the other infrastructure to properly deal with setting SSE, etc. features on X86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108677 91177308-0d34-0410-b5e6-96231b3b80d8
* llvmc: Add a new option type (switch_list).Mikhail Glushenkov2010-07-191-8/+43
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108673 91177308-0d34-0410-b5e6-96231b3b80d8
* Update comment.Bill Wendling2010-07-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108571 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename DBG_LABEL PROLOG_LABEL, because it's only used during prolog emission andBill Wendling2010-07-161-1/+1
| | | | | | | thus is a much more meaningful name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108563 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the entire docs directory from Apple-style builds.Bob Wilson2010-07-141-2/+2
| | | | | | | This fixes a "usr_junk" verification failure when installing into /usr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108384 91177308-0d34-0410-b5e6-96231b3b80d8
* Try to get embedded build of llvmCore to pass verification.Bob Wilson2010-07-142-17/+9
| | | | | | | Simplify some things in the process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108382 91177308-0d34-0410-b5e6-96231b3b80d8
* Silence a warning.Jakob Stoklund Olesen2010-07-121-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108169 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert some tab stops into spaces.Duncan Sands2010-07-123-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108130 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace copyRegToReg with COPY in FastISelEmitter.Jakob Stoklund Olesen2010-07-111-13/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108071 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman2010-07-101-2/+2
| | | | | | | | | | - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
* Start the support for AVX instructions with 256-bit %ymm registers. A couple ofBruno Cardoso Lopes2010-07-091-0/+2
| | | | | | | | | | | | | | | | | notes: - The instructions are being added with dummy placeholder patterns using some 256 specifiers, this is not meant to work now, but since there are some multiclasses generic enough to accept them, when we go for codegen, the stuff will be already there. - Add VEX encoding bits to support YMM - Add MOVUPS and MOVAPS in the first round - Use "Y" as suffix for those Instructions: MOVUPSYrr, ... - All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107996 91177308-0d34-0410-b5e6-96231b3b80d8
* --- Reverse-merging r107947 into '.':Bob Wilson2010-07-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
* These changes should have accompanied r107943.Dan Gohman2010-07-091-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107947 91177308-0d34-0410-b5e6-96231b3b80d8
* Changes to ARM tail calls, mostly cosmetic.Dale Johannesen2010-07-081-2/+2
| | | | | | | | | | | Add explicit testcases for tail calls within the same module. Duplicate some code to humor those who think .w doesn't apply on ARM. Leave this disabled on Thumb1, and add some comments explaining why it's hard and won't gain much. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107851 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 107840 107839 107813 107804 107800 107797 107791.Dan Gohman2010-07-081-2/+2
| | | | | | | Debug info intrinsics win for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the major chunk of PR7195: support for 'callw'Chris Lattner2010-07-072-0/+3
| | | | | | | | | in the integrated assembler. Still some discussion to be done. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107825 91177308-0d34-0410-b5e6-96231b3b80d8
* Give FunctionLoweringInfo an MBB member, avoiding the need to pass itDan Gohman2010-07-071-2/+2
| | | | | | | | | around everywhere, and also give it an InsertPt member, to enable isel to operate at an arbitrary position within a block, rather than just appending to a block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107791 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename "Release" builds as "Release+Asserts"; rename "Release-Asserts"Duncan Sands2010-07-071-2/+2
| | | | | | | | | | | | | | builds to "Release". The default build is unchanged (optimization on, assertions on), however it is now called Release+Asserts. The intent is that future LLVM releases released via llvm.org will be Release builds in the new sense, i.e. will have assertions disabled (currently they have assertions enabled, for a more than 20% slowdown). This will bring them in line with MacOS releases, which ship with assertions disabled. It also means that "Release" now means the same things in make and cmake builds: cmake already disables assertions for "Release" builds AFAICS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107758 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new target independent COPY instruction and code to lower it.Jakob Stoklund Olesen2010-07-021-0/+1
| | | | | | | | | | | The COPY instruction is intended to replace the target specific copy instructions for virtual registers as well as the EXTRACT_SUBREG and INSERT_SUBREG instructions in MachineFunctions. It won't we used in a selection DAG. COPY is lowered to native register copies by LowerSubregs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107529 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up TargetOpcodes.h a bit, and limit the number of places where the fullJakob Stoklund Olesen2010-07-022-88/+33
| | | | | | | | | list of predefined instructions appear. Add some consistency checks. Ideally, TargetOpcodes.h should be produced by TableGen from Target.td, but it is hardly worth the effort. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107520 91177308-0d34-0410-b5e6-96231b3b80d8
* Use -l option to remove symbols from i386.Bill Wendling2010-06-291-4/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107212 91177308-0d34-0410-b5e6-96231b3b80d8
* Strip resulting binaries.Bill Wendling2010-06-291-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107112 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused variables.Duncan Sands2010-06-251-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106834 91177308-0d34-0410-b5e6-96231b3b80d8
* Change array references to match my previous change to use the public typeBob Wilson2010-06-241-1/+1
| | | | | | | names for the array fields. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106803 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix up some comments.Bob Wilson2010-06-241-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106795 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the struct tags mandated by ARM's ABI. Also use the public type names forBob Wilson2010-06-241-4/+51
| | | | | | | the array fields in these structs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106794 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the x86 instructions "pusha" and "popa".Nico Weber2010-06-231-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106671 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a tblgen bug.Bruno Cardoso Lopes2010-06-231-1/+1
| | | | | | | | | | | | | | | | | | | Given the pattern below as an example: list<dag> Pattern = [(set RC:$dst, (v4f32 (shufp:src3 RC:$src1, (mem_frag addr:$src2))))]; The right reference resolving should lead to: list<dag> Pattern = [(set VR128:$dst, (v4f32 (shufp:src3 VR128:$src1, (mem_frag addr:$src2))))]; But was yielding: list<dag> Pattern = [(set VR128:$dst, (v4f32 (shufp VR128:$src1, (mem_frag addr:$src2))))]; Fix this by passing the right name when creating a new DagInit node. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106670 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't link against libm and libpthread which don't exist in BeOS/Haiku. Also,Nick Lewycky2010-06-233-4/+7
| | | | | | | Haiku like Linux provides <regex.h>, so use it. Patch by Paul Davey! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106620 91177308-0d34-0410-b5e6-96231b3b80d8
* Generate DWARF information during Apple-style build. They'll be stripped outBill Wendling2010-06-221-10/+16
| | | | | | | later on. But we need them saved in the symbols directory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106604 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a subtle multiclass bug: when using class inheritance onBruno Cardoso Lopes2010-06-221-4/+4
| | | | | | | | a toplevel 'defm', make sure to properly resolve references. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106570 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove isTwoAddress from llvm.Eric Christopher2010-06-211-11/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106470 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for returning multiple vectors via sret, which is how the ARM ↵Nate Begeman2010-06-201-30/+42
| | | | | | target expects the intrinsics to work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106406 91177308-0d34-0410-b5e6-96231b3b80d8
* An attempt to fix the problem Anton reported withDale Johannesen2010-06-181-0/+1
| | | | | | | | | ARM tail calls. Don't know if it works, but it doesn't break Darwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106309 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach tablegen how to inherit from classes in 'defm' definitions.Bruno Cardoso Lopes2010-06-181-0/+50
| | | | | | | | | The rule is simple: only inherit from a class list if they come in the end, after the last multiclass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106305 91177308-0d34-0410-b5e6-96231b3b80d8
* Start TargetRegisterClass indices at 0 instead of 1, so thatDan Gohman2010-06-182-2/+3
| | | | | | | | MachineRegisterInfo doesn't have to confusingly allocate an extra entry. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
* In case Rec is a definition and not a class, do the proper comparison!Bruno Cardoso Lopes2010-06-171-1/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106246 91177308-0d34-0410-b5e6-96231b3b80d8
* Modify tablegen to support generating all NEON code used by clang at once.Nate Begeman2010-06-172-89/+135
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106207 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the handling of !if result, avoiding null results for non 'int'.Bruno Cardoso Lopes2010-06-171-4/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106201 91177308-0d34-0410-b5e6-96231b3b80d8
* For a tablegen expression such as !if(a,b,c), let 'a'Bruno Cardoso Lopes2010-06-171-2/+4
| | | | | | | be evaluated for 'bit' operators git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106185 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the typo in my previous one-line commit.Sean Hunt2010-06-171-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106179 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure CMake can build the files added by my previous commit.Sean Hunt2010-06-161-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106178 91177308-0d34-0410-b5e6-96231b3b80d8
* Add preliminary clang attribute generation support.Sean Hunt2010-06-163-0/+147
| | | | | | | The attribute class generation support is still somewhat limited. See the accompanying clang commit for more details. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106174 91177308-0d34-0410-b5e6-96231b3b80d8
* let the '!eq' expression support 'int' and 'bit' typesBruno Cardoso Lopes2010-06-161-1/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106171 91177308-0d34-0410-b5e6-96231b3b80d8
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