aboutsummaryrefslogtreecommitdiffstats
path: root/utils
Commit message (Collapse)AuthorAgeFilesLines
* Move getSubRegIndex out of generated code into MCRegisterInfo, devirtualize it.Benjamin Kramer2012-03-011-11/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151821 91177308-0d34-0410-b5e6-96231b3b80d8
* Move TargetRegisterInfo::getSubReg() to MCRegisterInfo.Jim Grosbach2012-03-011-51/+56
| | | | | | | | Allows us to de-virtualize the function and provides access to it in the instruction printer, which is useful for handling composite physical registers (e.g., ARM register lists). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151815 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Emit the SubRegTable with the smallest possible integer type."Jim Grosbach2012-03-014-14/+11
| | | | | | | | | | This reverts commit 151760. We want to move getSubReg() from TargetRegisterInfo into MCRegisterInfo, but to do that, the type of the lookup table needs to be the same for all targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151814 91177308-0d34-0410-b5e6-96231b3b80d8
* Make TargetRegisterClasses non-virtual by making the only virtual function a ↵Benjamin Kramer2012-03-011-44/+41
| | | | | | | | | | | function pointer. This allows us to make TRC non-polymorphic and value-initializable, eliminating a huge static initializer and a ton of cruft from the generated code. Shrinks ARMBaseRegisterInfo.o by ~100k. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151806 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit the "is an intrinsic overloaded" table as a bitfield.Benjamin Kramer2012-03-011-7/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151792 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit the intrinsic modref info as a lookup table instead of a huge switch.Benjamin Kramer2012-03-011-16/+18
| | | | | | Shrinks BasicAliasAnalysis.o from 106k to 56k on i386. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151781 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement getSubRegIndex as a linear search on the SubRegTable instead of ↵Benjamin Kramer2012-02-291-14/+6
| | | | | | | | | using a big switch. - The search bounds are constant, in the worst case (ARM target) it will scan over 30 uint16_ts. - This method isn't very hot, I had problems finding a testcase where it's called more than a dozen of times (no perf impact). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151773 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. 80 columns.Jim Grosbach2012-02-292-14/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151764 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit the SubRegTable with the smallest possible integer type.Benjamin Kramer2012-02-294-11/+14
| | | | | | Doesn't help ARM with its massive register set, but halves the size on x86 and all other targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151760 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Spelling.Jim Grosbach2012-02-291-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151758 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the subregister indicies enum into the REGINFO_ENUM section.Jim Grosbach2012-02-291-15/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151756 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch TargetRegisterInfo::getSubReg() to use a lookup table.Jim Grosbach2012-02-291-18/+34
| | | | | | | | | | Instead of nested switch statements, use a lookup table. On ARM, this replaces a 23k (x86_64 release build) function with a 16k table. Its not unlikely to be faster, as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151751 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert generated intrinsic attributes to use an array lookup as Chris ↵Craig Topper2012-02-281-18/+26
| | | | | | suggested in PR11951. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151622 91177308-0d34-0410-b5e6-96231b3b80d8
* Update tblgen command guide. Remove unused tblgen InstrEnumEmitter files.Craig Topper2012-02-273-82/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151513 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by ↵Craig Topper2012-02-273-0/+16
| | | | | | Kay Tiong Khoo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151510 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove 'if' from getSuperRegisters, getSubRegisters, and getOverlaps that ↵Craig Topper2012-02-231-1/+1
| | | | | | were added in r151038. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151246 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove bad comma from .el file.Bill Wendling2012-02-221-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151189 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Foreach LoopDavid Greene2012-02-222-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add some data structures to represent for loops. These will be referenced during object processing to do any needed iteration and instantiation. Add foreach keyword support to the lexer. Add a mode to indicate that we're parsing a foreach loop. This allows the value parser to early-out when processing the foreach value list. Add a routine to parse foreach iteration declarations. This is separate from ParseDeclaration because the type of the named value (the iterator) doesn't match the type of the initializer value (the value list). It also needs to add two values to the foreach record: the iterator and the value list. Add parsing support for foreach. Add the code to process foreach loops and create defs based on iterator values. Allow foreach loops to be matched at the top level. When parsing an IDValue check if it is a foreach loop iterator for one of the active loops. If so, return a VarInit for it. Add Emacs keyword support for foreach. Add VIM keyword support for foreach. Add tests to check foreach operation. Add TableGen documentation for foreach. Support foreach with multiple objects. Support non-braced foreach body with one object. Do not require types for the foreach declaration. Assume the iterator type from the iteration list element type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151164 91177308-0d34-0410-b5e6-96231b3b80d8
* Declare register classes as const. Fix a couple pointers to register classes ↵Craig Topper2012-02-221-3/+4
| | | | | | that weren't already const. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151138 91177308-0d34-0410-b5e6-96231b3b80d8
* Make all pointers to TargetRegisterClass const since they are all pointers ↵Craig Topper2012-02-221-2/+2
| | | | | | to static data that should not be modified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
* Reorder some members in MCRegisterClass to remove padding on 64-bit builds.Craig Topper2012-02-211-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151043 91177308-0d34-0410-b5e6-96231b3b80d8
* In generated RegisterInfo files, replace a pointer to the end of an array ↵Craig Topper2012-02-211-4/+2
| | | | | | with just the size of the array to avoid relocations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151041 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge some tables in generated RegisterInfo file. Store indices into larger ↵Craig Topper2012-02-211-28/+48
| | | | | | table instead of pointers to reduce relocations and shrink table size on 64-bit builds. Shaves ~24K off X86MCTargetDesc.o. Accidentally commited only part of this in r151038. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151039 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead code. Improve llvm_unreachable text. Simplify some control flow.Ahmed Charles2012-02-192-48/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150918 91177308-0d34-0410-b5e6-96231b3b80d8
* Add vmfunc instruction to X86 assembler and disassembler.Craig Topper2012-02-191-8/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150899 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86 assembler and disassembler support for AMD SVM instructions. ↵Craig Topper2012-02-182-1/+11
| | | | | | Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150873 91177308-0d34-0410-b5e6-96231b3b80d8
* utils: Kill NewNightlyTest.pl, which has been replaced by LNT (as far as I ↵Daniel Dunbar2012-02-152-842/+3
| | | | | | know). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150610 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the EDis tables const.Benjamin Kramer2012-02-111-5/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150304 91177308-0d34-0410-b5e6-96231b3b80d8
* Reuse the enum names from X86Desc in the X86Disassembler.Benjamin Kramer2012-02-111-1/+1
| | | | | | | This requires some gymnastics to make it available for C code. Remove the names from the disassembler tables, making them relocation free. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150303 91177308-0d34-0410-b5e6-96231b3b80d8
* Put instruction names into an indexed string table on the side, removing a ↵Benjamin Kramer2012-02-101-2/+20
| | | | | | | | | pointer from MCInstrDesc. Make them accessible through MCInstrInfo. They are only used for debugging purposes so this doesn't have an impact on performance. X86MCTargetDesc.o goes from 630K to 461K on x86_64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150245 91177308-0d34-0410-b5e6-96231b3b80d8
* Store just the SimpleValueType in the generated VT tables for each register ↵Benjamin Kramer2012-02-091-1/+1
| | | | | | class, eliminating static ctors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150173 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the Name field in MCInstrDesc to the end, saving 8 bytes of padding per ↵Benjamin Kramer2012-02-091-2/+3
| | | | | | | | entry on x86_64. No change on i386. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150170 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the MC and disassembler about SoftFail, and hook it up to ↵James Molloy2012-02-091-2/+76
| | | | | | UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150169 91177308-0d34-0410-b5e6-96231b3b80d8
* More tweaks to get the size of the X86 disassembler tables down.Craig Topper2012-02-091-7/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150167 91177308-0d34-0410-b5e6-96231b3b80d8
* Flatten some of the arrays in the X86 disassembler tables to reduce space ↵Craig Topper2012-02-091-38/+38
| | | | | | needed to store pointers on 64-bit hosts and reduce relocations needed at startup. Part of PR11953. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150161 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't map registers to the invalid dwarf register (-1). It's the default value.Benjamin Kramer2012-02-081-0/+3
| | | | | | | X86GenRegisterInfo.inc | 1032 ------------------------------------------------- 1 file changed, 1032 deletions(-) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150080 91177308-0d34-0410-b5e6-96231b3b80d8
* Value initialize MCRegisterClasses. Not sure how could miss this during the ↵Benjamin Kramer2012-02-081-2/+2
| | | | | | MCTargetDesc refactor. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150076 91177308-0d34-0410-b5e6-96231b3b80d8
* This is a small patch with a couple of improvements for running lit with ↵Andrew Trick2012-02-062-2/+9
| | | | | | | | | | | | | --debug: 1. Added a status note when a config file is loaded directly with load_config. This helps notice loads of lit.cfg from lit.site.cfg 2. Added a status note on the result of a config load. Previously, it was just notifying that it tries to load a config file. Now it will also say whether the load succeeded or the file wasn't found The two changes give better visibility into which config files were actually loaded by lit. The effect is only on --debug runs. Patch by Eli Bendersky! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149932 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-0511-41/+33
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149814 91177308-0d34-0410-b5e6-96231b3b80d8
* Increment DFAStateEntryTable index for sentinel entry.Brendon Cahoon2012-02-031-1/+3
| | | | | | | | | | When adding the {-1, -1} entry to the DFAStateInputTable, we need to increment the index used to populate the DFAStateEntryTable. Otherwise, the entry table will be off by one for each transition after the {-1, -1} entry. PR11908. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149713 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the old --with-cxx-* configure options with a single ↵Rafael Espindola2012-02-031-8/+6
| | | | | | | | | --with-gcc-toolchain that just uses the new toolchain probing logic. This fixes linking with -m32 on 64 bit systems (the /32 dir was not being added to the search). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149651 91177308-0d34-0410-b5e6-96231b3b80d8
* Specify SubRegIndex components on the index itself.Jakob Stoklund Olesen2012-02-012-25/+77
| | | | | | | | | | | | | | | | | It is simpler to define a composite index directly: def ssub_2 : SubRegIndex<[dsub_1, ssub_0]>; def ssub_3 : SubRegIndex<[dsub_1, ssub_1]>; Than specifying the composite indices on each register: CompositeIndices = [(ssub_2 dsub_1, ssub_0), (ssub_3 dsub_1, ssub_1)] in ... This also makes it clear that SubRegIndex composition is supposed to be unique. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149556 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in the TopoOrderRC comparison function.Jakob Stoklund Olesen2012-02-011-1/+1
| | | | | | | | | | | The final tie breaker comparison also needs to return +/-1, or 0. This is not a less() function. This could cause otherwise identical super-classes to be ordered unstably, depending on what the system qsort routine does with a bad compare function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149549 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid emitting empty arrays, they're not standard C++.Jakob Stoklund Olesen2012-02-011-6/+11
| | | | | | | It's only by luck that we haven't produced any yet, and clang refuses to compile them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149546 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't assign a value to NUM_TARGET_NAMED_SUBREGS.Jakob Stoklund Olesen2012-01-311-2/+1
| | | | | | It was wrong and completely unused. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149433 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the composite map into CodeGenSubRegIndex.Jakob Stoklund Olesen2012-01-313-30/+51
| | | | | | Each SubRegIndex keeps track of how it composes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149423 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a TableGen CodeGenSubRegIndex class.Jakob Stoklund Olesen2012-01-313-64/+144
| | | | | | | | | This class is used to represent SubRegIndex instances instead of the raw Record pointers that were used before. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149418 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove Deprecated FeaturesDavid Greene2012-01-271-250/+51
| | | | | | | | | | | | Move to a model where we build whatever branches are checked out in the source directories. This was a bit too smart (and complicated) in handling details best left to the user and the revision control system. In addition, get rid of support for llvm-gcc and building gcc as these are no longer necessary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149149 91177308-0d34-0410-b5e6-96231b3b80d8
* Use -H on darwin as well.Eric Christopher2012-01-261-1/+1
| | | | | | Patch by Liang Wang! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149085 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Trailing whitespace.Jim Grosbach2012-01-241-24/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148856 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-01-27 03:11:57 +0000