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* Soften the pattern-can-never-match error in TableGen into a warning. This ↵Owen Anderson2012-09-191-2/+5
| | | | | | pattern can be very useful in cases where you want to define a multiclass that covers both commutative and non-commutative operators (say, add and sub). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164256 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove code for setting the VEX L-bit as a function of operand size from the ↵Craig Topper2012-09-192-19/+2
| | | | | | code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164204 91177308-0d34-0410-b5e6-96231b3b80d8
* SchedMachineModel: compress the CPU's WriteLatencyTable.Andrew Trick2012-09-193-7/+44
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164199 91177308-0d34-0410-b5e6-96231b3b80d8
* Iterate deterministicaly over ClassInfo*'sSean Silva2012-09-191-2/+12
| | | | | | | | Fixes an observed instance of nondeterministic TableGen output. Review by Jakob. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164191 91177308-0d34-0410-b5e6-96231b3b80d8
* Iterate deterministically over register classesSean Silva2012-09-191-2/+3
| | | | | | | | Fixes an observed instance of nondeterministic TableGen output. Review by Jakob. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164190 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor Record* by-ID comparator to Record.hSean Silva2012-09-192-18/+9
| | | | | | | | | | | This is a generally useful utility; there's no reason to have it hidden in CodeGenDAGPatterns.cpp. Also, rename it to fit the other comparators in Record.h Review by Jakob. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164189 91177308-0d34-0410-b5e6-96231b3b80d8
* FileCheck: Fix off-by-one bug that made CHECK-NOT: ignore the next character ↵Benjamin Kramer2012-09-181-2/+2
| | | | | | after the colon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164165 91177308-0d34-0410-b5e6-96231b3b80d8
* Make custom operand parsing mnemonic indices use the same mnemonic table as ↵Craig Topper2012-09-181-34/+39
| | | | | | the match table. Reorder fields in OperandMatchEntry to provide the least amount of padding for in tree targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164109 91177308-0d34-0410-b5e6-96231b3b80d8
* Use variable type for index into mnemonic table. Shrinks size of index field ↵Craig Topper2012-09-181-5/+14
| | | | | | on in tree targets. Saving static data space. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164108 91177308-0d34-0410-b5e6-96231b3b80d8
* Replaced ReInitMCSubtargetInfo with InitMCProcessor.Andrew Trick2012-09-181-1/+2
| | | | | | | | Now where we used to call ReInitMCSubtargetInfo, we actually recompute the same information as InitMCSubtargetInfo instead of only setting the feature bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164105 91177308-0d34-0410-b5e6-96231b3b80d8
* comment typoAndrew Trick2012-09-181-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164097 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen subtarget emitter. Use getSchedClassIdx.Andrew Trick2012-09-182-11/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164096 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen subtarget emitter. Generate resolveSchedClass generated hook for ↵Andrew Trick2012-09-181-0/+84
| | | | | | resolving instruction variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164095 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen subtarget emitter. Remove unnecessary header dependence.Andrew Trick2012-09-181-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164094 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick2012-09-181-6/+25
| | | | | | model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164092 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark asm matcher conversion table as const.Craig Topper2012-09-181-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164088 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo in comment. No functional change.Craig Topper2012-09-181-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164086 91177308-0d34-0410-b5e6-96231b3b80d8
* Backout the wrong subtarget emitter fixAndrew Trick2012-09-171-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164078 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix release build after revertingAndrew Trick2012-09-171-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164075 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r164061-r164067. Most of the new subtarget emitter.Andrew Trick2012-09-173-113/+20
| | | | | | | | I have to work out the Target/CodeGen header dependencies before putting this back. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164072 91177308-0d34-0410-b5e6-96231b3b80d8
* InitMCProcessorAndrew Trick2012-09-171-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164066 91177308-0d34-0410-b5e6-96231b3b80d8
* comment typoAndrew Trick2012-09-171-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164064 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen subtarget emitter. Use getSchedClassIdx.Andrew Trick2012-09-172-11/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164063 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen subtarget emitter. Generate resolveSchedClass generated hook for ↵Andrew Trick2012-09-171-0/+84
| | | | | | resolving instruction variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164062 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine ↵Andrew Trick2012-09-171-7/+25
| | | | | | model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164061 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen subtarget emitter. Format and emit data tables for the new machine ↵Andrew Trick2012-09-171-6/+117
| | | | | | model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164060 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen subtarget emitter. Generate data tables for the new machine model.Andrew Trick2012-09-171-2/+291
| | | | | | | | | | | | Map the CodeGenSchedule object model onto data tables. The structure of the data tables is defined in MC, so for convenience we include MCSchedule.h. The alternative is maintaining a redundant copy of the table structure definitions. Mapping the object model onto data tables is sufficiently complicated that it should not be interleaved with emitting source code. This avoids major problem with the backend for itinerary generation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164059 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen subtarget emitter. Emit processor resources for the new machine model.Andrew Trick2012-09-171-10/+63
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164058 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen subtarget parser: Add getProcResourcesIdx().Andrew Trick2012-09-171-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164057 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: Add initializer.Jim Grosbach2012-09-171-1/+1
| | | | | | | Keep GCC's warnings happy. It can't reason out that the state machine won't ever hit the potentially uninitialized use in OPC_FilterValue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164041 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a few vars that can end up being used without initialization.Axel Naumann2012-09-171-1/+1
| | | | | | | The cases where no initialization happens should still be checked for logic flaws. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164032 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typoMichael Liao2012-09-171-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164012 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 'virtual' keywoards to output file for overridden functions.Craig Topper2012-09-161-5/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164002 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 'virtual' keywoards to output file for overridden functions.Craig Topper2012-09-161-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163999 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Doxygen issues: wrap code examples in \code and use \p to refer toDmitri Gribenko2012-09-151-4/+4
| | | | | | | parameters. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163984 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r163878 as it breaks on targets with alternate register names. Such ↵Craig Topper2012-09-152-6/+4
| | | | | | targets do not exist in the main tree so this was not noticed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163959 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen subtarget parser. Handle new machine model.Andrew Trick2012-09-152-0/+219
| | | | | | Collect processor resources from the subtarget defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163953 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen subtarget parser. Handle new machine model.Andrew Trick2012-09-152-0/+512
| | | | | | Infer SchedClasses from variants defined by the target or subtarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163952 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen subtarget parser. Handle new machine model.Andrew Trick2012-09-153-137/+816
| | | | | | Collect SchedClasses and SchedRW types from the subtarget defs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163951 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow the second opcode info table to be 8, 16, or 32-bits as needed to ↵Craig Topper2012-09-141-38/+32
| | | | | | represent additional fragments. This recovers some space on ATT X86 syntax and PowerPC which only need 40-bits instead of 48-bits. This also increases ARM to 64-bits to fully encode all of its operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163880 91177308-0d34-0410-b5e6-96231b3b80d8
* Reduce size of register name index tables by using uint16_t for all in tree ↵Craig Topper2012-09-142-4/+6
| | | | | | targets. If more than 16-bits are needed for any out of tree targets, code will detect and use uint32_t instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163878 91177308-0d34-0410-b5e6-96231b3b80d8
* AsmWriterEmitter: OpInfo2 should be unsigned 16-bit.Manman Ren2012-09-131-1/+1
| | | | | | | Fix an issue in r163814. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163837 91177308-0d34-0410-b5e6-96231b3b80d8
* AsmWriterEmitter: increase the number of bits for OpcodeInfo from 32-bit toManman Ren2012-09-131-11/+46
| | | | | | | | | | | | 48-bit if necessary, in order to reduce the generated code size. We have 900 cases not covered by OpcodeInfo in ATT AsmWriter and more in Intel AsmWriter and ARM AsmWriter. This patch reduced the clang Release build size by 50k, running on a Mac Pro. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163814 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix Doxygen issues:Dmitri Gribenko2012-09-132-20/+21
| | | | | | | | | * wrap code blocks in \code ... \endcode; * refer to parameter names in paragraphs correctly (\arg is not what most people want -- it starts a new paragraph). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163790 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new compression type to ModRM table that detects when the memory modRM ↵Craig Topper2012-09-131-2/+15
| | | | | | byte represent 8 instructions and the reg modRM byte represents up to 64 instructions. Reduces modRM table from 43k entreis to 25k entries. Based on a patch from Manman Ren. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163774 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen: Convert an assert() to a proper diagnostic.Jim Grosbach2012-09-121-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163726 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a couple of Doxygen comment issues pointed out by -Wdocumentation.Dmitri Gribenko2012-09-121-20/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163721 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve tblgen code cleanliness: create an unknown_class, from which the ↵Owen Anderson2012-09-112-3/+3
| | | | | | unknown def inherits. Make tblgen check for that class, rather than checking for the def itself. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163664 91177308-0d34-0410-b5e6-96231b3b80d8
* Compute a map from register names to registers, rather than scanning the ↵Owen Anderson2012-09-113-6/+15
| | | | | | list of registers every time we want to look up a register by name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163659 91177308-0d34-0410-b5e6-96231b3b80d8
* Add TRI::getSubRegIndexLaneMask().Jakob Stoklund Olesen2012-09-113-6/+68
| | | | | | | | | | | | | | | | | Sub-register lane masks are bitmasks that can be used to determine if two sub-registers of a virtual register will overlap. For example, ARM's ssub0 and ssub1 sub-register indices don't overlap each other, but both overlap dsub0 and qsub0. The lane masks will be accurate on most targets, but on targets that use sub-register indexes in an irregular way, the masks may conservatively report that two sub-register indices overlap when the eventually allocated physregs don't. Irregular register banks also mean that the bits in a lane mask can't be mapped onto register units, but the concept is similar. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163630 91177308-0d34-0410-b5e6-96231b3b80d8
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